Automatic multi-objective optimization of parameters for hardware and code optimizations

Jahr, Ralf; Ungerer, Theo; Calborean, Horia; Vintan, Lucian

doi:10.1109/hpcsim.2011.5999839

Cited by 10 publications

(20 citation statements)

References 19 publications

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“…The array is arranged in row and columns of ALUs (see the Figure. 1 [2]). Every column in the array is assigned to a single top register in the original GAP architecture.…”

Section: Grid Alu Processormentioning

confidence: 99%

“…For calculation of clock cycles, we use a simulator program. We write the simulator in java programming language based on descriptions about GAP that represented in [1,2,14,15,16]. This simulator would be described in section IV.…”

Section: Calculation Of Parametersmentioning

confidence: 99%

“…For calculation of design complexity we use (3) [2,16]: In (3) C X presents complexity of element X ∈ {ALUs, Load/Store, Cache}. The values of C ALUs, C LSUs, C cache are respectively calculates from (4), (5) and (6).…”

Section: Calculation Of Parametersmentioning

confidence: 99%

“…The GAP combines elements of superscalar processor architectures with a coarsegrained reconfigurable array of functional units [2]. GAP architecture contains a two-dimensional Functional Units (FUs).…”

Section: Grid Alu Processormentioning

confidence: 99%

“…For parallel execution of sequential programs we need processors that change sequence of instructions to execute Independent instructions together. One of processors that raise parallel execution of instructions is Grid ALU processor that called GAP [2]. This processor has features of superscalar and reconfigurable systems with an array of Functional Units (FUs) to execute instructions simultaneously that reorder by a configure unit.…”

Section: Introductionmentioning

confidence: 99%

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Multi Objective Design Space Exploaration for Grid ALU Processor

Asgari

2012

IJESA

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Todays billions of transistors allow architects to design different huge processor to increasing parallel execution of instructions, which leads to increasing complexity of architecture. Establishing a trade-off between the complexity and performance to finding optimal design is a big challenge. In this paper we are going to focus on the design space exploration the Grid ALU Processor (GAP) to finding optimal design for it.To do so we address a multi-objective optimization method based on Pareto Front. This method helps us find best configuration of GAP at maximum performance and minimum complexity.

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“…The array is arranged in row and columns of ALUs (see the Figure. 1 [2]). Every column in the array is assigned to a single top register in the original GAP architecture.…”

Section: Grid Alu Processormentioning

confidence: 99%

Section: Calculation Of Parametersmentioning

confidence: 99%

Section: Calculation Of Parametersmentioning

confidence: 99%

Section: Grid Alu Processormentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Multi Objective Design Space Exploaration for Grid ALU Processor

Asgari

2012

IJESA

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Finding near‐perfect parameters for hardware and code optimizations with automatic multi‐objective design space explorations

Jahr

Calborean

Vintan

et al. 2012

Concurrency and Computation

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SummaryIn the design process of computer systems or processor architectures, typically many different parameters are exposed to configure, tune, and optimize every component of a system. For evaluations and before production, it is desirable to know the best setting for all parameters. Processing speed is no longer the only objective that needs to be optimized; power consumption, area, and so on have become very important. Thus, the best configurations have to be found in respect to multiple objectives. In this article, we use a multi‐objective design space exploration tool called Framework for Automatic Design Space Exploration (FADSE) to automatically find near‐optimal configurations in the vast design space of a processor architecture together with a tool for code optimizations and hence evaluate both automatically. As example, we use the Grid ALU Processor (GAP) and its postlink optimizer called GAPtimize, which can apply feedback‐directed and platform‐specific code optimizations. Our results show that FADSE is able to cope with both design spaces. Less than 25% of the maximal reasonable hardware effort for the scalable elements of the GAP is enough to achieve the processor's performance maximum. With a performance reduction tolerance of 10%, the necessary hardware complexity can be further reduced by about two‐thirds. The found high‐quality configurations are analyzed, exhibiting strong relationships between the parameters of the GAP, the distribution of complexity, and the total performance. These performance numbers can be improved by applying code optimizations concurrently to optimizing the hardware parameters. FADSE can find near‐optimal configurations by effectively combining and selecting parameters for hardware and code optimizations in a short time. The maximum observed speedup is 15%. With the use of code optimizations, the maximum possible reduction of the hardware resources, while sustaining the same performance level, is 50%.Copyright © 2012 John Wiley & Sons, Ltd.

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