Automatic generation of nested, fork-join parallelism

Burke, Michael G.; Cytron, Ron K.; Ferrante, Jeanne; Hsieh, Wilson C.

doi:10.1007/bf00129843

Cited by 38 publications

(15 citation statements)

References 17 publications

(13 reference statements)

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“…It may be possible, however, to transform programs so they contain more intrinsic parallelism. For example, scientific application parallelism strategies often leverage privatization [4] to enhance parallelism. Basic transformations such as privatization, accumulator expansion, or other techniques which expose the order agnostic nature of many algorithms may create more opportunities for parallelism.…”

Section: A Baseline Performancementioning

confidence: 99%

Chip multi-processor scalability for single-threaded applications

Vachharajani

Iyer

Ashok

et al. 2005

SIGARCH Comput. Archit. News

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The exponential increase in uniprocessor performance has begun to slow. Designers have been unable to scale performance while managing thermal, power, and electrical effects. Furthermore, design complexity limits the size of monolithic processors that can be designed while keeping costs reasonable. Industry has responded by moving toward chip multi-processor architectures (CMP). These architectures are composed from replicated processors utilizing the die area afforded by newer design processes. While this approach mitigates the issues with design complexity, power, and electrical effects, it does nothing to directly improve the performance of contemporary or future single-threaded applications.This paper examines the scalability potential for exploiting the parallelism in single-threaded applications on these CMP platforms. The paper explores the total available parallelism in unmodified sequential applications and then examines the viability of exploiting this parallelism on CMP machines. Using the results from this analysis, the paper forecasts that CMPs, using the "intrinsic" parallelism in a program, can sustain the performance improvement users have come to expect from new processors for only 6-8 years provided many successful parallelization efforts emerge. Given this outlook, the paper advocates exploring methodologies which achieve parallelism beyond this "intrinsic" limit of programs.

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Section: A Baseline Performancementioning

confidence: 99%

Chip multi-processor scalability for single-threaded applications

Vachharajani

Iyer

Ashok

et al. 2005

SIGARCH Comput. Archit. News

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Section: Preliminariesmentioning

confidence: 99%

A scalable method for run-time loop parallelization

Rauchwerger

Amato

Padua³

1995

Int J Parallel Prog

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Current parallelizing compilers do a reasonable job of extracting parallelism from programs with regular, well behaved, statically analyzable access patterns. However, they cannot extract a significant fraction of the available parallelism if the program has a complex and/or statically insufficiently defined access pattern, e.g., simulation programs with irregular domains and/or dynamically changing interactions. Since such programs represent a large fraction of all applications, techniques are needed for extracting their inherent parallelism at run-time. In this paper we give a new run-time technique for finding an optimal parallel execution schedule for a partially parallel loop, i.e., a loop whose parallelization requires synchronization to ensure that the iterations are executed in the correct order. Given the original loop, the compiler generates inspector code that performs run-time preprocessing of the loop's access pattern, and scheduler code that schedules (and executes) the loop iterations. The inspector is fully parallel, uses no synchronization, and can be applied to any loop (from which an inspector can be extracted). In addition, it can implement at run-time the two most effective transformations for increasing the amount of parallelism in a loop: array privatization and reduction parallelization (element-wise). The ability to identify privatizable and reduction variables is very powerful since it eliminates the data dependences involving these variables and thereby potentially increases the overall parallelism of the loop. We also describe a new scheme for constructing an optimal parallel execution schedule for the iterations of the loop. The schedule produced is a partition of the set of iterations into subsets called wavefronts so that there are no data dependences between iterations in a wavefront. Although the wavefronts themselves are constructed one after another, the computation of each wavefront is fully parallel and requires no synchronization. This new method has advantages over all previous run-time techniques for analyzing and scheduling partially parallel loops since none of them has all of these desirable properties.

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“…Privatization creates, for each processor cooperating on the execution of the loop, private copies of the program variables that give rise to anti or output dependences (see, e.g., [7,18,19,31]). The loop shown in Figure 1(a), is an example of a loop that can be executed in parallel by using privatization; the anti dependences between statement S2 of iteration i and statement S1 of iteration i + 1 , for 1 i n = 2 , can be removed by privatizing the temporary variable tmp.…”

Section: Preliminariesmentioning

confidence: 99%

Run-time methods for parallelizing partially parallel loops

Rauchwerger

Amato

Padua

1995

Proceedings of the 9th International Conference on Supercomputing - ICS '95

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In this paper we give a new run-time technique for finding an optimal parallel execution schedule for a partially parallel loop, i.e., a loop whose parallelization requires synchronization to ensure that the iterations are executed in the correct order. Given the original loop, the compiler generates inspector code that performs run-time preprocessing of the loop's access pattern, and scheduler code that schedules (and executes) the loop iterations. The inspector is fully parallel, uses no synchronization, and can be applied to any loop. In addition, it can implement at run-time the two most effective transformations for increasing the amount of parallelism in a loop: array privatization and reduction parallelization (element-wise). We also describe a new scheme for constructing an optimal parallel execution schedule for the iterations of the loop.

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Automatic generation of nested, fork-join parallelism

Cited by 38 publications

References 17 publications

Chip multi-processor scalability for single-threaded applications

Chip multi-processor scalability for single-threaded applications

A scalable method for run-time loop parallelization

Run-time methods for parallelizing partially parallel loops

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