Automatic generation of memory built-in self-repair circuits in SOCs for minimizing test time and area cost

Design and Implementation of Repair-aware Test Flow for Multi-Memory

“…In order to reduce the test time and make test and repair easier, the memories under test are divided into more than one test sessions [6]. The memories in the same test session can be tested simultaneously, using a distributed BIST structure.…”

“…Since our overall test flow based on the memory grouping strategy presented in section II, after the post repair (including test and repair procedures), it can be significant to improve the yield of chips. Before we discuss post repair stage, it is necessary to give the conception of feasible region of the memory block and test session in order to get more effective understanding of this stage [6]. Generally, we assume that the selecting algorithm, which selects one or more memory blocks to repair itself or others in the same test session, uses either horizontal or vertical segments in the two-dimension (2D) layer , and the central point of square is origin.…”

“…That is, we choose the minimal distance for use. Many such selecting algorithms are available in literature [6].…”

“…It can significantly improve the yield of the memory blocks. In [6], the author mainly concerns on how to minimize the test time and area cost by using automatic generation of memory BISR circuity and uses memory grouping techniques which only used for BISR to manage the BISR circuits.One contribution of this paper is that we present a grouping method to go through the overall test flow including BIST and BISR, and another important contribution is that we use a gated selecting technology, gating off some unnecessarily memories to reduce the power consumption, to select some memory blocks that need to re-test. Section 2 presents the details of test flow and memory grouping strategy used in this paper.…”