Automatic generation of application-specific architectures for heterogeneous multiprocessor system-on-chip

Lyonnard, D.; Yoo, Sungjoo; Baghdadi, Amer; Jerraya, Ahmed

doi:10.1145/378239.379015

Cited by 115 publications

(53 citation statements)

References 20 publications

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“…Finally, a body of work on interface synthesis and design [31]- [37] addresses issues related to implementation of specified protocols in hardware, and enables component reusability. Once the mapping of the system components to a communication architecture has been performed, these techniques help generate the interface logic between pairs of communicating components.…”

Section: B Related Workmentioning

confidence: 99%

Design Space Exploration for Optimizing On-Chip Communication Architectures

Lahiri

Raghunathan

Dey

2004

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

100

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Rapid growth in the complexity of system-on-chips is being accompanied by increasing volume and diversity of on-chip communication traffic, which in turn, is driving the development of advanced system-level communication architectures. While these architectures have the potential to improve system performance, they pose significant new challenges to the system designer, owing to the complex design space defined by the availability of numerous network topologies, communication protocols, and mapping alternatives for system communications. In this paper, we address the problem of mapping a system's communication requirements to a given communication architecture template. We illustrate the nature of the communication architecture design space, and describe an exploration methodology that uses efficient algorithms to help automate the process of mapping the system communications to the selected template. In addition, we demonstrate the importance of simultaneously optimizing the on-chip communication protocols in order to maximize system performance. Experiments conducted on example systems, including a cell forwarding unit of an ATM switch, indicate that the proposed techniques aid in automatically constructing communication architectures that have high performance. For the systems we considered, the solutions generated using our methodology had 53% superior performance (on average), over those based on conventional architectures and mapping approaches. The algorithms used in the proposed methodology are computationally efficient, and scale well with increasing communication architecture complexity.

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Section: B Related Workmentioning

confidence: 99%

Design Space Exploration for Optimizing On-Chip Communication Architectures

Lahiri

Raghunathan

Dey

2004

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

100

View full text Add to dashboard Cite

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“…In terms of implementation, the HW wrapper is a processor interface that connects the processor to the communication network at micro-architecture level (for further details, refer to [9]). The SW wrapper is an OS that enables the application SW to perform inter/intra-processor communication (for further details, refer to [7]).…”

Section: Aggregate Timing Model Of Osmentioning

confidence: 99%

“…Wrappers are constructed in the form of software (SW), i.e. operating system (OS) 1 [7] as well as in the form of hardware (HW) [8] [9].…”

Section: Introductionmentioning

confidence: 99%

Automatic generation of fast timed simulation models for operating systems in SoC design

Yoo¹,

Nicolescu²,

Gauthier³

et al.

Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition

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To enable fast and accurate evaluation of HW/SW implementation choices of on-chip communication, we present a method to automatically generate timed OS simulation models. The method generates the OS simulation models with the simulation environment as a virtual processor. Since the generated OS simulation models use final OS code, the presented method can mitigate the OS code equivalence problem. The generated model also simulates different types of processor exceptions. This approach provides two orders of magnitude higher simulation speedup compared to the simulation using instruction set simulators for SW simulation.

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“…It is then not surprising that few works so far have been devoted to design methodologies for multiprocessors on chip. In [7] they present a design flow for the generation of applicationspecific multiprocessor architectures. In the flow architectural parameters are first extracted from a high-level specification and are used to instantiate architectural components such as processors, memory modules and communication networks.…”

Section: Previous Workmentioning

confidence: 99%

System-Level Design Methodology with Direct Execution For Multiprocessors on SoPC

Mouhoub

Hammami

7th International Symposium on Quality Electronic Design (ISQED'06)

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Contrary to ASIC design where resources can be tuned with respect to the need of the designer, systems on programmable chip SoPC (FPGA) have to make best use of 'off the shelf devices', where main resources are fixed. In this regard, embedded memories are of tremendous value because of their low latency. These embedded memories are not only used for data and program storage but also for all sorts of memory usage e.g. FIFO used by IP interfaces for bus and network on chip connection. The problem addressed by this paper is the optimal sizing of queues in the framework of SoPC. Current SoC design tools are of little help to define the most adequate size for these FIFOs and the large design space coupled with excessive simulation times make it even more difficult. We propose in this paper an automatic tuning technique of queue sizes in IP interfaces for system on programmable chip with hardware in the loop execution. An application of our technique on Virtex-II SoPC is described.

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Automatic generation of application-specific architectures for heterogeneous multiprocessor system-on-chip

Cited by 115 publications

References 20 publications

Design Space Exploration for Optimizing On-Chip Communication Architectures

Design Space Exploration for Optimizing On-Chip Communication Architectures

Automatic generation of fast timed simulation models for operating systems in SoC design

System-Level Design Methodology with Direct Execution For Multiprocessors on SoPC

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