Automatic Formal Correspondence Checking of ISA and RTL Microprocessor Description

HADES: Microprocessor Hazard Analysis via Formal Verification of Parameterized Systems

“…Compared with [6,7,8], we enriched the number of variants for the above introduced processors, which gave us 17 unique test cases in total. The variants of the particular processors differ in the following aspects: (i) the way how data hazards are avoided (pipeline stalling and clearing, data bypassing), (ii) the presence of flag / status registers, and (iii) utilization of so-called auto-increment (AI) logic.…”

“…Here, the main idea is that, this way, a high degree of automation and scalability can be achieved since only parts of a design related to a specific error are to be investigated. The above idea has been followed, e.g., in the works [6,7] that proposed fully automated approaches for (1) checking correctness of individual execution of processor instructions and (2) for verifying absence of read-after-write (RAW) hazards when the instructions are pipelined. In [8], the approach was extended by covering write-after-write (WAW) and write-after-read (WAR) hazards.…”

Configurable Verification Stimulus Acceleration Method Based on Multicore Processor

“…Equivalence checking [11] is used to prove that the two design models have the same function, which is actually the most widely used formal verification technology, such as Cadence's Conformal and Synopsys's Formality. Model checking [12,13] is used to prove that a design meets certain attributes, such as Cadence's Formal Checker. Theorem proving requires the user deep understanding of the basic logic and formal proof, which is costly and rarely used.…”