Automatic Floorplanning for AI SoCs

Chen, Tai-Chen; Lee, Pei-Yu; Chen, Tung-Chieh

doi:10.1109/vlsi-dat49148.2020.9196464

Cited by 8 publications

(3 citation statements)

References 5 publications

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“…These kind of integrated platforms needed floor planning ideas that adopt deep learning and artificial intelligence blocks with mixer macro and cell placement complexities. The presented system discuss in detail on the logical interconnects and the complexities of numerous macros in SOCs [24]. Complex placement regions in electrostatic systems based modeling are discussed.…”

Section: Scholarly Articlesmentioning

confidence: 99%

Ca & Sbo : A Novel Optimized Placement Algorithms for an Efficient Vlsi Design

2023

Preprint

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Designing a simplest architecture involves appropriate placement, which is often, regarded as a critical concerns of physical design engineers. Placement and routing of chips in automated manner is been research since decades and provides better predictive performance than manual procedures. However, most of the automated models operating under meta-heuristic optimization fails in obtaining optimal solution due to premature convergence and non-optimal placement of solutions. In this paper, we develop a novel meta-heuristic optimization method namely Cellular Automata (CA) and Satin Bowerbird Optimization (SBO) that combines Primal-dual lagrangian technique (SimPL) and Complex Primal dual lagrangian (ComPL) for attaining optimal placement and routing of chips. The process of CA and SBO optimization approach operates on obtaining optimized placement solutions from the SimPL and ComPL solutions. The combination of CA-SimPL, SBO-SimPL, CA-ComPL and SBO-ComPL is implemented on electronic design automation (EDA) tools with python simulator for pre-training and fine-tuning the optimization model. The simulation is conducted on a high-end computing system to test the computational time speed up ratio on different threads and half-perimeter wire length (HWPL). The results of simulation shows that the proposed models obtain increased performance with reduced computational time than other methods.

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Section: Scholarly Articlesmentioning

confidence: 99%

Ca & Sbo : A Novel Optimized Placement Algorithms for an Efficient Vlsi Design

2023

Preprint

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“…We find that the number of clusters impacts the correlation of the computed reward before and after clustering. Therefore, we select the top 20 ranking macro placements from an industry placer [27] that can output multiple candidate results for each circuit to analyze the most suitable cluster number for each circuit. Fig.…”

Section: Reward Computationmentioning

confidence: 99%

Flexible Multiple-Objective Reinforcement Learning for Chip Placement

Chang¹,

Tseng²,

Yang³

et al. 2022

Preprint

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Recently, successful applications of reinforcement learning to chip placement have emerged. Pretrained models are necessary to improve efficiency and effectiveness. Currently, the weights of objective metrics (e.g., wirelength, congestion, and timing) are fixed during pretraining. However, fixed-weighed models cannot generate the diversity of placements required for engineers to accommodate changing requirements as they arise. This paper proposes flexible multiple-objective reinforcement learning (MORL) to support objective functions with inference-time variable weights using just a single pretrained model. Our macro placement results show that MORL can generate the Pareto frontier of multiple objectives effectively.

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“…A machine learningbased timing characterization is a potential solution to the above challenge [18]. Support vector machine (SVM) and artificial neural network (ANN) are few of the regression-based machine learning algorithms that can be exploited to correct the path-based timing violations to improve the accuracy [19].…”

Section: Machine Learning In Static Timimg Analysis (Sta)mentioning

confidence: 99%

Machine Learning Perspective in VLSI Computer-Aided Design at Different Abstraction Levels

Bansal

Priya

2021

Mobile Computing and Sustainable Informatics

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In the past few decades, machine learning, a subset of artificial intelligence (AI), has emerged as a disruptive technology which is now being extensively used and has stretched across various domains. Among the numerous applications, one of the most significant advancements due to Machine Learning is in the field of Very Large Scale Integrated Circuits (VLSI). Further growth and improvements in this field are highly anticipated in the near future. The fabrication of thousands of transistors in VLSI is time consuming and complex which demanded the automation of design process, and hence, computer-aided design (CAD) tools and technologies have started to evolve. The incorporation of machine learning in VLSI involves the application of machine learning algorithms at different abstraction levels of VLSI CAD. In this paper, we summarize several machine learning algorithms that have been developed and are being widely used. We also have briefly discussed about how machine learning methods have transuded the layers of VLSI design process from register transfer level (RTL) assertion generation to static timing analysis (STA) with smart and efficient models and methodologies, further enhancing the quality of chip design with power, performance and area improvements and complexity and turnaround time reduction.

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Automatic Floorplanning for AI SoCs

Cited by 8 publications

References 5 publications

Ca & Sbo : A Novel Optimized Placement Algorithms for an Efficient Vlsi Design

Ca & Sbo : A Novel Optimized Placement Algorithms for an Efficient Vlsi Design

Flexible Multiple-Objective Reinforcement Learning for Chip Placement

Machine Learning Perspective in VLSI Computer-Aided Design at Different Abstraction Levels

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Automatic Floorplanning for AI SoCs

Cited by 8 publications

References 5 publications

Ca &amp; Sbo : A Novel Optimized Placement Algorithms for an Efficient Vlsi Design

Ca &amp; Sbo : A Novel Optimized Placement Algorithms for an Efficient Vlsi Design

Flexible Multiple-Objective Reinforcement Learning for Chip Placement

Machine Learning Perspective in VLSI Computer-Aided Design at Different Abstraction Levels

Contact Info

Product

Resources

About

Ca & Sbo : A Novel Optimized Placement Algorithms for an Efficient Vlsi Design

Ca & Sbo : A Novel Optimized Placement Algorithms for an Efficient Vlsi Design