Automatic Fault Detection Circuit for Integrated Gate Drivers of Active-Matrix Displays

Abstract

This paper presents automatic fault detection circuit for integrated gate drivers. The proposed circuit consists of one capacitor and two TFTs per scan line. The circuit can detect three types of faults, such as line disconnection (LD), low voltage stuck (LVS), and high voltage stuck (HVS) for the gate driver due to external physical stress. Simulation results showed the proposed circuit operates well. In order to verify the circuit operation, it was fabricated with indium gallium zinc oxide thin film transistors process. The measurement results also verified that our proposed fault detection circuit could detect the types and locations of the LD and LVS of the gate driver successfully. However, we found that HVS can be detected, but further study is needed to accurately detect the position of HVS in the proposed circuit.INDEX TERMS Fault detection, stretchable display, gate driver circuits.

Fault-Tolerant Architecture for Reliable Integrated Gate Drivers

“…Fig. 3 shows simulated results when a gate driver operated normally in the previous study [15]. We can distinguish the types of faults when we carefully investigate V READ during vertical blank.…”

“…Our proposed FT gate driver uses the fault detection circuit which we proposed in the previous study [15]. Fig.…”

“…In this paper, we propose a FT gate driver that can automatically repair the fault when it happens at a specific stage of gate driver due to physical stress during display driving. The proposed circuit uses redundant circuit structure with fault detection circuit [15]. Although this architecture brings increase in circuit area, it is much less expensive than destroying a whole display panel with fault and also improves lifetime of display products.…”

25‐3: Fault‐Tolerant Integrated Gate Driver for Flexible Displays

“…Unlike a carry-type gate driver circuit, a decoder-type gate driver operates independently stage by stage [6]. In addition, we add the fault detection circuit [7] and redundant unit to achieve faulttolerant architecture. Figure 1 shows circuit diagram and timing diagram of unit stage of proposed gate driver circuit.…”

“…The threshold level of gate output voltage which triggers the circuits can be programmed. Detail of the detection circuit is in our previous works [7].…”