Automatic enhanced CDFG generation based on runtime instrumentation

Zhong, Yang; Ma, Yuchun; Bian, Jinian; Zhao, Kang

doi:10.1109/cscwd.2013.6580945

Cited by 3 publications

(1 citation statement)

References 28 publications

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“…Dynamic profiles are dependent on the input data set. Dynamic profiling has already been used in high level synthesis domain to generate better solutions than static approaches [8,9]. Similarly, our work also shows that dynamic profiling has generated better solutions than static profiling in application specific VLIW processor tailoring.…”

Section: Introductionmentioning

confidence: 49%

Customizing VLIW processors from dynamically profiled execution traces

Malazgirt

Yurdakul²,

Niar³

2015

Microprocessors and Microsystems

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Section: Introductionmentioning

confidence: 49%

Customizing VLIW processors from dynamically profiled execution traces

Malazgirt

Yurdakul²,

Niar³

2015

Microprocessors and Microsystems

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Methods for Change Parallelism in Process of High-level VLSI Synthesis

Ryzhenko

Nepomnyashchiy

Legalov³

et al. 2022

Model. anal. inf. sist.

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In this paper methods for increasing the efficiency of VLSI development based on the method of architecture-independent design are proposed. The route of high-level VLSI synthesis is considered. The principle of constructing a VLSI hardware model based on the functional-flow programming paradigm is stated.The results of the development of methods and algorithms for transformation functional-parallel programs into programs in HDL languages that support the design process of digital chips are presented. The principles of assessment are considered and the classes of resources required for the analysis of design solutions are identified. Reduction coefficients and methods of their calculation for each resource class have been introduced. An algorithm for calculating the reduction coefficients and estimating the required resources is proposed. An algorithm for converting parallelism is proposed, taking into account the specified constraints of the target platform. A mechanism for the exchange of metrics with an architecture-dependent level has been developed. Examples of parallelism reduction for the FPGA platform and practical implementation of FFT algorithms in the Virtex® UltraScale FPGA basis are given. The developed methods and algorithms make it possible to use the method of architecture-independent synthesis for transferring VLSI projects to various architectures by changing the parallelism of the circuit and equivalent transformations of parallel programs. The proposed approach provides many options for hardware solutions for implementation on various target platforms.

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