Automatic defect severity scoring for 193-nm reticle defect inspection

Karklin, Linard; Altamirano, Mark M.; Cai, Lynn; Phan, Khoi A.; Spence, Chris

doi:10.1117/12.435716

Cited by 9 publications

(10 citation statements)

References 2 publications

(4 reference statements)

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“…However, AIMS TM depends on traditional inspection tools to detect the defects in question, as has been previously demonstrated [ 2]. Other tools used for qualifying reticles with aerial images are software tools used to simulate the expected aerial image, based on a reticle image; these simulations depend similarly on the inspection tools to find the defects [ 3].…”

Section: Aerial Imaging Inspection Conceptmentioning

confidence: 98%

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Aerial image-based inspection of binary (OPC) and embedded-attenuated PSM

et al. 2002

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The paper presents a revolutionary technology to inspect advanced contact layers. Instead of finding defects based on a size-dependent defect specification, defects are found according to their impact at the wafer CD result. The inspection methodology used is aerial imaging. The main advantage of this method is that only defects, which actually affect the wafer result, will be detected and classified. The paper presents first inspection results on contact layers designed for the 130nm and 90 nm technology node.

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Section: Aerial Imaging Inspection Conceptmentioning

confidence: 98%

“…The most prominent one is AIMS TM [1][2][3][4], most commonly used for final qualification of reticles after repair. AIMS TM is considered a reliable tool for defect dispositioning and many studies in the past have shown compatibility between printability and AIMS TM imaging [ 1].…”

Section: Aerial Imaging Inspection Conceptmentioning

confidence: 99%

Aerial image-based inspection of binary (OPC) and embedded-attenuated PSM

et al. 2002

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“…the change in drive current caused by this defect, which is then used as a pessimistic approximation of change in cell delay as shown in (2). Assuming that at most K defects lie on a critical path, 6 we can evaluate the minimum defect size that changes the delay of each affected transistor by less than T slack /K and hence ensure timing correctness of the path. Here, the timing slack must be obtained from a timing report that designers need to pass on to mask shops.…”

Section: A Polysilicon Layermentioning

confidence: 99%

“…Defect disposition is done only on the basis on printability that is determined using software tools like Virtual Stepper [5], [6] along with AIMS emulation [8]. It assumes that all printable defects larger than a threshold size (say 10% of mask CD) are critical.…”

Section: B Related Workmentioning

confidence: 99%

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Design-Aware Mask Inspection

Kagalwalla

Gupta

Progler

et al. 2012

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Mask inspection has become a major bottleneck in the manufacturing flow taking up as much as 40% of the total mask manufacturing time. In this paper, we explore techniques to improve the reticle inspection flow by increasing its design awareness. We develop an algorithm to locate nonfunctional features in a postoptical proximity correction layout without using any design information. Using this, and the timing information of the design (if available), the smallest defect size that could cause the design to fail is assigned to each reticle feature. The criticality of various reticle features is then used to partition the reticle such that each partition is inspected at a different pixel size and sensitivity so that the false and nuisance defect count is reduced without missing any critical defect. We also develop an analytical model to estimate the false and nuisance defect count. Using those models, our simulation results show that this designaware mask inspection can reduce the false and nuisance defect count for a critical polysilicon layer from 80 defects down to 49 defects, leading to substantial reduction in defect review load. We also develop a model to estimate first pass yield (FPY) and show that our method can improve the FPY for a polysilicon layer from 11% to 30%. Apart from the polysilicon layer, the potential benefit of this approach is analyzed for active, contact and all the metal/via layers.Index Terms-Computer-aided design (CAD), design for manufacturability (DFM), mask inspection, mask manufacturing, reticle, semiconductor manufacturing.

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Defect printability analysis study using virtual stepper system in a production environment

et al. 2002

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In this paper, the simulation of wafer images for Attenuated Phase Shift Masks (ATTPSM) and repaired binary masks are performed by Virtual Stepper® System in a real production environment. In addition, the Automatic Defect Severity Scoring (ADSS) module in Virtual Stepper is also used to calculate the defect severity score for each defect. ADSS provides an overall score that quantifies the impact of a given defect on the surrounding features. For the binary masks, the quality of repaired defects is studied. For the ATTPSM, three types of programmed defects (protrusion, intrusion, and pin-dot) on both line/space and contact hole patterns are assessed. Wafer exposures are performed using 248 nm imaging technology and inspection images generated on a KLA -Tencofs SLF27 system. These images are used by the Virtual Stepper System to simulate wafer images under the specific stepper parameters. The results are compared to SEM images ofresist patterns and Aerial Image Measurement System (AIMSTM) simulated results.

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Automatic defect severity scoring for 193-nm reticle defect inspection

Cited by 9 publications

References 2 publications

Aerial image-based inspection of binary (OPC) and embedded-attenuated PSM

Aerial image-based inspection of binary (OPC) and embedded-attenuated PSM

Design-Aware Mask Inspection

Defect printability analysis study using virtual stepper system in a production environment

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