Automatic Defect Cluster Extraction for Semiconductor Wafers

Ooi, Melanie Po-Leen; Sim, Eric; Kuang, Ye Chow; Kleeman, Lindsay; Chan, Chris; Demidenko, Serge

doi:10.1109/imtc.2010.5488012

Cited by 15 publications

(3 citation statements)

References 8 publications

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“…It is therefore important to identify the defects in the wafer early in the manufacturing process so that the process can be improved to reduce time and yield loss. It has been observed that the defects generally occur in clusters in a wafer in certain locations (Ooi et al, 2010). A kernel‐based method to detect such clusters is proposed in Sumikawa, Nero, and Wang (2017).…”

Section: Yield Learning and Diagnosismentioning

confidence: 99%

A survey of digital circuit testing in the light of machine learning

Pradhan

Bhattacharya

2020

WIREs Data Min & Knowl

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The insistent trend in today's nanoscale technology, to keep abreast of the Moore's law, has been continually opening up newer challenges to circuit designers. With rapid downscaling of integration, the intricacies involved in the manufacturing process have escalated significantly. Concomitantly, the nature of defects in silicon chips has become more complex and unpredictable, adding further difficulty in circuit testing and diagnosis. The volume of test data has surged and the parameters that govern testing of integrated circuits have increased not only in dimension but also in the complexity of their correlation. Evidently, the current scenario serves as a pertinent platform to explore new test solutions based on machine learning. In this survey, we look at various recent advances in this evolving domain in the context of digital logic testing and diagnosis. This article is categorized under: Algorithmic Development > Structure Discovery Technologies > Machine Learning Technologies > Prediction

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Section: Yield Learning and Diagnosismentioning

confidence: 99%

A survey of digital circuit testing in the light of machine learning

Pradhan

Bhattacharya

2020

WIREs Data Min & Knowl

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“…The mainstream research on WBM analysis has focused on the discovery of meaningful patterns or clusters from bad wafers. In this framework, bad wafers are manually filtered first, and then various analytical techniques are applied to find significant patterns or clusters based on their WBMs [16][17][18][19][20]. In the early 2000s, Huang et al [16] found wafer clusters by applying a 3 × 3 median filter to the WBM to replace isolated chips with the median value of neighboring chips.…”

Section: Literature Reviewmentioning

confidence: 99%

“…In the 2010s, Ooi et al [18] proposed the segmentation with detection and small cluster removal (SDC) algorithm. The SDC algorithm automatically generated features for clustering WBMs by local yield conversion (LYC) method, which extracted the mean value of the "passed" and "failed" neighboring chips around the targeted chip.…”

Section: Literature Reviewmentioning

confidence: 99%

Bin2Vec: A Better Wafer Bin Map Coloring Scheme for Comprehensible Visualization and Effective Bad Wafer Classification

Kim

Park

et al. 2019

Applied Sciences

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A wafer bin map (WBM), which is the result of an electrical die-sorting test, provides information on which bins failed what tests, and plays an important role in finding defective wafer patterns in semiconductor manufacturing. Current wafer inspection based on WBM has two problems: good/bad WBM classification is performed by engineers and the bin code coloring scheme does not reflect the relationship between bin codes. To solve these problems, we propose a neural network-based bin coloring method called Bin2Vec to make similar bin codes are represented by similar colors. We also build a convolutional neural network-based WBM classification model to reduce the variations in the decisions made by engineers with different expertise by learning the company-wide historical WBM classification results. Based on a real dataset with a total of 27,701 WBMs, our WBM classification model significantly outperformed benchmarked machine learning models. In addition, the visualization results of the proposed Bin2Vec method makes it easier to discover meaningful WBM patterns compared with the random RGB coloring scheme. We expect the proposed framework to improve both efficiencies by automating the bad wafer classification process and effectiveness by assigning similar bin codes and their corresponding colors on the WBM.

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