Automatic code generation for distributed memory architectures in the polytope model

Abstract

Abstract-The polytope model has been used successfully as a tool for program analysis and transformation in the field of automatic loop parallelization. However, for the final step of automatic code generation, the generated code is either only usable on shared memory architectures or severely restricts the parallelization methods that can be applied. In this paper, we present a fully automated method for generating efficient target code, which is executable on clusters that are based on a distributed memory architecture. We also provide speedup results of experiments on a local cluster.

Analytical synthesis of bandwidth-efficient SDRAM address generators

“…While there is extensive research [5,8,12] considering reordering of the statements within a loop nest for improved performance, we propose a different approach; preserving the original execution order, we propose the introduction of scratchpad memory (reuse buffers) at levels within the loop body. The memory buffer can be introduced at any level within the loop nest, we define a parameter 1 6 t 6 n to describe the placement of the buffer within a n-level loop nest.…”

“…Scheduling and loop transformations which alter the execution order within this polytope framework have been extensively studied [5,8,12] either to expose parallelism by eliminating loop carried dependencies, or to reduce the communications cost when partitioning code across many processors in a HPC system.…”

Application Specific Memory Access, Reuse and Reordering for SDRAM

“…Scheduling and loop transformations which alter the execution order within this polytope framework have been extensively studied [11,7,4] either to expose parallelism by eliminating loop carried dependencies, or to reduce the communications cost when partitioning code across many processors in a HPC system.…”

“…While the work in [11,7,4] considers reordering the statements within a loop nest, we propose a different approach; preserving the original execution order, we propose the introduction of memory buffers (reuse buffers) at levels within the loop body. Unlike caches, which are filled by an implicit hardware mechanism, these memories are explicitly populated with data using code derived from the original problem description.…”

“…If this code is evaluated with the initial indices (i = 0, j = 0), an address (R = 2) and a further two indices i = 1, j = 0 are generated. When these are iteratively evaluated using the same function, the sequence of addresses (2,4,6,8) is generated. This is exactly the memory addresses touched by the original input code, presented in a strictly increasing order and with all repetition removed.…”