Automatic cache partitioning and time-triggered scheduling for real-time MPSoCs

Chen, Gang; Hu, Bi Ying; Huang, Kai; Knoll, Alois; Liu, Di; Stefanov, Todor

doi:10.1109/reconfig.2014.7032502

Cited by 8 publications

(7 citation statements)

References 22 publications

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“…This paper summarizes and extends the results built in [26]. In this cache architecture, the cache resources are strictly isolated to prevent the cache interference among cores.…”

Section: Introductionmentioning

confidence: 67%

Reconfigurable cache for real-time MPSoCs: Scheduling and implementation

Chen

Huang

et al. 2016

Microprocessors and Microsystems

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Shared cache in modern multi-core systems has been considered as one of the major factors that degrade system predictability and performance. How to manage the shared cache for real-time multi-core systems in order to optimize the system performance while guaranteeing the system predictability is an open issue. In this paper, we present a reconfigurable cache architecture which supports dynamic cache partitioning at hardware level and a framework that can exploit cache management for real-time MPSoCs. The proposed reconfigurable cache allows cores to dynamically allocate cache resource with minimal timing overhead while guaranteeing strict cache isolation among the real-time tasks. The cache management framework automatically determines time-triggered schedule and cache configuration for each task to minimize cache misses while guaranteeing the real-time constraints. We evaluate the proposed framework with respect to different numbers of cores and cache modules and prototype the constructed MPSoCs on FPGA. Our experiments show that, our automatic framework brings significant benefits over the state-of-the-art cache management strategies when testing 27 benchmark programs on the constructed MPSoCs.

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“…This paper summarizes and extends the results built in [26]. In this cache architecture, the cache resources are strictly isolated to prevent the cache interference among cores.…”

Section: Introductionmentioning

confidence: 67%

Reconfigurable cache for real-time MPSoCs: Scheduling and implementation

Chen

Huang

et al. 2016

Microprocessors and Microsystems

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“…To solve this problem, we implement multicore cache management in hardware level and propose an integrated cache management scheme that improves the execution predictability for MPSoCs. This paper summarizes the results built in [1].…”

Section: Introductionmentioning

confidence: 86%

Abstract: Shared L2 Cache Management in Multicore Real-Time System

Chen¹,

Hu²,

Huang³

et al. 2014

2014 IEEE 22nd Annual International Symposium on Field-Programmable Custom Computing Machines

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In multicore system, shared cache interference has been recognized as one of the major factors that degrade the average performance as well as predictability of system. How to manage the shared cache in order to optimize the system performance while guaranteeing the system predictability is still an open issue. State-of-the-art techniques on this topic use page coloring to partition the shared cache at OS level. In this paper, we present a shared cache management scheme for multicore system. This shared cache management scheme supports way-based cache partitioning at hardware level, building task-level timetriggered reconfigurable-cache multicore system. We evaluated the proposed scheme w.r.t. different numbers of cores and cache modules and prototyped the constructed MPSoCs on FPGA.

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“…Chen et al do a lot of work on dynamic cache partitioning on real-time MPSoCs. [16][17][18] They present a recon¯gurable cache architecture which supports dynamic cache partitioning at hardware level and a framework that can exploit cache management for real-time MPSoCs. The proposed recon¯gurable cache allows cores to dynamically allocate cache resource with minimal timing overhead while guaranteeing strict cache isolation among the real-time tasks.…”

Section: Cache Partitioningmentioning

confidence: 99%

A Performance Conserving Approach for Reducing Memory Power Consumption in Multi-Core Systems

Fang

Wang

et al. 2019

J CIRCUIT SYST COMP

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With more cores integrated into a single chip and the fast growth of main memory capacity, the DRAM memory design faces ever increasing challenges. Previous studies have shown that DRAM can consume up to 40% of the system power, which makes DRAM a major factor constraining the whole system’s growth in performance. Moreover, memory accesses from different applications are usually interleaved and interfere with each other, which further exacerbates the situation in memory system management. Therefore, reducing memory power consumption has become an urgent problem to be solved in both academia and industry. In this paper, we first proposed a novel strategy called Dynamic Bank Partitioning (DBP), which allocates banks to different applications based on their memory access characteristics. DBP not only effectively eliminates the interference among applications, but also fully takes advantage of bank level parallelism. Secondly, to further reduce power consumption, we propose an adaptive method to dynamically select an optimal page policy for each bank according to the characteristics of memory accesses that each bank receives. Our experimental results show that our strategy not only improves the system performance but also reduces the memory power consumption at the same time. Our proposed scheme can reduce memory power consumption up to 21.2% (10% on average across all workloads) and improve the performance to some extent. In the case that workloads are built with mixed applications, our scheme reduces the power consumption by 14% on average and improves the performance up to 12.5% (3% on average).

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Automatic cache partitioning and time-triggered scheduling for real-time MPSoCs

Cited by 8 publications

References 22 publications

Reconfigurable cache for real-time MPSoCs: Scheduling and implementation

Reconfigurable cache for real-time MPSoCs: Scheduling and implementation

Abstract: Shared L2 Cache Management in Multicore Real-Time System

A Performance Conserving Approach for Reducing Memory Power Consumption in Multi-Core Systems

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