Automatic Application-Specific Calibration to Enable Dynamic Voltage Scaling in FPGAs

Ahmed, Ibrahim; Zhao, Shuze; Trescases, Olivier; Betz, Vaughn

doi:10.1109/tcad.2018.2801222

“…Undervolting on real FPGAs is not thoroughly investigated. Very recent works on FPGA undervolting are either accompanied with frequency underscaling [1,103] that can diminish performance, or are limited to BRAMs [95,96,97,99,91]. This paper, for the first time, extends real FPGA undervolting studies to multiple on-chip components of modern FPGA fabrics and evaluates it in-detail on the power-accuracy trade-off of CNN applications.…”

Section: Undervoltingmentioning

confidence: 99%

“…Older generations of Xilinx FPGAs like the 7-series are not equipped with this capability [121]. Thus, for such older devices, BRAM power consumption was the main source of FPGA power consumption, as shown in previous studies [96,97,99,1]. For the rest of the paper, as we study the power-reliability trade-off, we concentrate on V CCINT due to its dominance in FPGA power consumption.…”

Section: Power Analysis Of Fpga-based Cnn Accelerators At the Nominal Voltage Level (V Nom )mentioning

confidence: 99%

“…In this paper, we characterize the power dissipation of FPGA-based CNN accelerators under reduced-voltage levels and apply undervolting to improve the power-efficiency of such accelerators. 1 We experimentally evaluate the effects of reduced-voltage operation in on-chip components of the FPGA platform, including Block RAMs (BRAMs) and internal FPGA components, containing Look-Up Tables (LUTs), Digital Signal Processors (DSPs), buffers, and routing resources. 2 We perform our experiments on five state-of-the-art CNN image classification benchmarks, including VGGNet [106], GoogleNet [110], AlexNet [51], ResNet [35], and Inception [110].…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

An Experimental Study of Reduced-Voltage Operation in Modern FPGAs for Neural Network Acceleration

Salami¹,

Onural

²

,

Yüksel

³

et al. 2020

2020 50th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN)

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We empirically evaluate an undervolting technique, i.e., underscaling the circuit supply voltage below the nominal level, to improve the power-efficiency of Convolutional Neural Network (CNN) accelerators mapped to Field Programmable Gate Arrays (FPGAs). Undervolting below a safe voltage level can lead to timing faults due to excessive circuit latency increase. We evaluate the reliability-power trade-off for such accelerators. Specifically, we experimentally study the reduced-voltage operation of multiple components of real FPGAs, characterize the corresponding reliability behavior of CNN accelerators, propose techniques to minimize the drawbacks of reduced-voltage operation, and combine undervolting with architectural CNN optimization techniques, i.e., quantization and pruning. We investigate the effect of environmental temperature on the reliability-power trade-off of such accelerators.We perform experiments on three identical samples of modern Xilinx ZCU102 FPGA platforms with five state-of-the-art image classification CNN benchmarks. This approach allows us to study the effects of our undervolting technique for both software and hardware variability. We achieve more than 3X power-efficiency (GOPs/W ) gain via undervolting. 2.6X of this gain is the result of eliminating the voltage guardband region, i.e., the safe voltage region below the nominal level that is set by FPGA vendor to ensure correct functionality in worst-case environmental and circuit conditions. 43% of the power-efficiency gain is due to further undervolting below the guardband, which comes at the cost of accuracy loss in the CNN accelerator. We evaluate an effective frequency underscaling technique that prevents this accuracy loss, and find that it reduces the power-efficiency gain from 43% to 25%.

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“…At present, the energy optimized technology for embedded systems is at different levels, including the circuit level, system level, storage level, and compile level [9]. At the system level, there are two primary energy-efficient approaches to address the energy consumption optimization: dynamic voltage and frequency scaling (DVFS) [10][11][12] and dynamic power management (DPM) [13,14]. These approaches are mainly the combination of task scheduling, DVFS, and DPM.…”

Section: Introductionmentioning

confidence: 99%

A Group-Based Energy-Efficient Dual Priority Scheduling for Real-Time Embedded Systems

Ge

¹

,

Liu

²

2020

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As the limitation of energy consumption of real-time embedded systems becomes more and more strict, it has been difficult to ignore the time overhead and energy consumption of context switches for fixed-priority tasks with preemption scheduling (FPP) in multitasking environments. In addition, the scheduling for different types of tasks may disrupt each other and affect system reliability. A group-based energy-efficient dual priority scheduling (GEDP) is proposed in this paper. The GEDP isolates different types of tasks to avoid the disruption. Furthermore, it also reduces context switches effectively, thus decreasing system energy consumption. As many studies ignored the context switches’ overhead in the worst-case response time (WCRT) model, and it will affect the accuracy of WCRT, thereby affecting the system schedulability. Consequently, the WCRT model is improved based on considering context switches’ overhead. The GEDP is designed and implemented in Linux, and the time overhead and energy consumption of context switches is compared in different situations with GEDP and FPP. The experimental results show that GEDP can reduce context switches by about 1% and decrease energy consumption by about 0.6% for given tasks.

show abstract

“…In this paper, we characterize the power dissipation of FPGA-based CNN accelerators under reduced-voltage levels and apply undervolting to improve the power-efficiency of such accelerators. 1 We experimentally evaluate the effects of reduced-voltage operation in on-chip components of the FPGA platform, including Block RAMs (BRAMs) and internal FPGA components, containing Look-Up Tables (LUTs), Digital Signal Processors (DSPs), buffers, and routing resources. 2 We perform our experiments on five state-of-the-art CNN image classification benchmarks, including VGGNet [106], GoogleNet [110], AlexNet [51], ResNet [35], and Inception [110].…”

Section: Introductionmentioning

confidence: 99%

An Experimental Study of Reduced-Voltage Operation in Modern FPGAs for Neural Network Acceleration

Salami¹,

Onural²,

Yüksel³

et al. 2020

Preprint

View full text Add to dashboard Cite

We empirically evaluate an undervolting technique, i.e., underscaling the circuit supply voltage below the nominal level, to improve the power-efficiency of Convolutional Neural Network (CNN) accelerators mapped to Field Programmable Gate Arrays (FPGAs). Undervolting below a safe voltage level can lead to timing faults due to excessive circuit latency increase. We evaluate the reliability-power trade-off for such accelerators. Specifically, we experimentally study the reduced-voltage operation of multiple components of real FPGAs, characterize the corresponding reliability behavior of CNN accelerators, propose techniques to minimize the drawbacks of reduced-voltage operation, and combine undervolting with architectural CNN optimization techniques, i.e., quantization and pruning. We investigate the effect of environmental temperature on the reliability-power trade-off of such accelerators.We perform experiments on three identical samples of modern Xilinx ZCU102 FPGA platforms with five state-of-the-art image classification CNN benchmarks. This approach allows us to study the effects of our undervolting technique for both software and hardware variability. We achieve more than 3X power-efficiency (GOPs/W ) gain via undervolting. 2.6X of this gain is the result of eliminating the voltage guardband region, i.e., the safe voltage region below the nominal level that is set by FPGA vendor to ensure correct functionality in worst-case environmental and circuit conditions. 43% of the power-efficiency gain is due to further undervolting below the guardband, which comes at the cost of accuracy loss in the CNN accelerator. We evaluate an effective frequency underscaling technique that prevents this accuracy loss, and find that it reduces the power-efficiency gain from 43% to 25%.

show abstract

Automatic Application-Specific Calibration to Enable Dynamic Voltage Scaling in FPGAs

Cited by 10 publications

References 26 publications

An Experimental Study of Reduced-Voltage Operation in Modern FPGAs for Neural Network Acceleration

An Experimental Study of Reduced-Voltage Operation in Modern FPGAs for Neural Network Acceleration

A Group-Based Energy-Efficient Dual Priority Scheduling for Real-Time Embedded Systems

An Experimental Study of Reduced-Voltage Operation in Modern FPGAs for Neural Network Acceleration

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