Automatic and Simultaneous Floorplanning and Placement in Field-Programmable Gate Arrays With Dynamic Partial Reconfiguration Based on Genetic Algorithm

Sadeghi, Ali; Lighvan, ‪Mina Zolfy; Prinetto, P.

doi:10.1109/cjece.2019.2962147

Cited by 5 publications

(2 citation statements)

References 31 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The re-positioning of these clocked modules in the floorplan results in geometric violations and increases the pre-defined width of the voltage island. This may lead to changes in the placement of modules in the neighboring voltage island that increases the routing resource in terms of wirelength [27,28]. For the purpose of quality floorplanning and to satisfy the voltage island constraint, we propose an algorithm to determine the optimal dimensions of the clocked modules in the voltage island.…”

Section: Problem Formulationmentioning

confidence: 99%

An Investigation of Clock Skew Using a Wirelength-Aware Floorplanning Process in the Pre-Placement Stages of MSV Layouts

Srinath¹,

Verma

Barnawi

et al. 2021

Electronics

View full text Add to dashboard Cite

Managing the timing constraints has become an important factor in the physical design of multiple supply voltage (MSV) integrated circuits (IC). Clock distribution and module scheduling are some of the conventional methods used to satisfy the timing constraints of a chip. In this paper, we propose a simulated annealing-based MSV floorplanning methodology for the design of ICs within the timing budget. Additionally, we propose a modified SKB tree representation for floorplanning the modules in the design. Our algorithm finds the optimal dimensions and position of the clocked modules in the design to reduce the wirelength and satisfy the timing constraints. The proposed algorithm is implemented in IWLS 2005 benchmark circuits and considers power, wirelength, and timing as the optimization parameters. Simulation results were obtained from the Cadence Innovus digital system taped-out at 45 nm. Our simulation results show that the proposed algorithm satisfies timing constraints through a 30.6% reduction in wirelength.

show abstract

Section: Problem Formulationmentioning

confidence: 99%

An Investigation of Clock Skew Using a Wirelength-Aware Floorplanning Process in the Pre-Placement Stages of MSV Layouts

Srinath¹,

Verma

Barnawi

et al. 2021

Electronics

View full text Add to dashboard Cite

show abstract

“…A floor plan should be developed based on the design space and takes into account a variety of modules, such as macros used to represent memory, design, and IP cores, as well as their space requirements. The aspect ratio, as well as the IO architecture, is considered while designing the floors (Shunmugathammal et al 2020b) (Giorgini et al 2018;Wang et al 2020;Sadeghi et al 2020). If the floor plan would be of poor quality, there's also a risk of routing bottleneck and dying area wastage (Prakash and Lal 2021).…”

Section: Introductionmentioning

confidence: 99%

Very Large-Scale Integration Floor Planning on FIR and Lattice Filters Design With Multi-Objective Hybrid Optimization

Pondreti

Kaparapu

2023

International Journal of Swarm Intelligence Research

View full text Add to dashboard Cite

Floor planning is indeed an obvious design process in VLSI physical layout since it specifies the dimensions, structure, as well as positions of components upon the chip; in addition, information regarding the overarching silicon area, interlinks, and latency is also provided. VLSI floor planning is an NP-hard issue as the floor plan representations are a crucial component in this process. The intricacy, as well as solution space of the floor plan layout, is influenced by the floorplan visualizations. To tackle the VLSI floor plan challenge, numerous researchers have developed numerous meta-heuristic optimization techniques. The main objective of this work presents a novel multi-objective hybrid optimization method for solving the floor plan optimization issue. Standard DOX and ALO are conceptually combined in the proposed hybrid optimization referred to as Dingo Updated Ant Lion Optimization (DUALO) model. The multi-objectives like wire length, area, and penalty function are taken into consideration.

show abstract

Strengthening evolution-based differential evolution with prediction strategy for multimodal optimization and its application in multi-robot task allocation

Zhao

Tang

et al. 2023

Applied Soft Computing

View full text Add to dashboard Cite

Automatic and Simultaneous Floorplanning and Placement in Field-Programmable Gate Arrays With Dynamic Partial Reconfiguration Based on Genetic Algorithm

Cited by 5 publications

References 31 publications

An Investigation of Clock Skew Using a Wirelength-Aware Floorplanning Process in the Pre-Placement Stages of MSV Layouts

An Investigation of Clock Skew Using a Wirelength-Aware Floorplanning Process in the Pre-Placement Stages of MSV Layouts

Very Large-Scale Integration Floor Planning on FIR and Lattice Filters Design With Multi-Objective Hybrid Optimization

Strengthening evolution-based differential evolution with prediction strategy for multimodal optimization and its application in multi-robot task allocation

Contact Info

Product

Resources

About