Automated Tool and Runtime Support for Fine-Grain Reconfiguration in Highly Flexible Reconfigurable Systems

Zamacola, Rafael; Martínez, Alberto García; Mora, Javier; Otero, Andrés; Torre, Eduardo de la

doi:10.1109/fccm.2019.00048

Cited by 2 publications

(4 citation statements)

References 1 publication

Supporting

Mentioning

Contrasting

Order By: Relevance

“…This value is incremented if any offspring chromosome improves the performance of the original one (line 12). A chromosome is removed if its age is over the maximum age, defined as an algorithm parameter (lines [13][14][15]. This mechanism prevents the stalling of the evolutionary algorithm.…”

Section: Proposed Evolutionary Algorithmmentioning

confidence: 99%

“…Its modular design and the distributed nature of its control make the BbNN an excellent candidate to be implemented in a grid-based RR, using specific reconfigurable interfaces. The proposed implementation is possible thanks to the use of the advanced reconfiguration features provided by the IMPRESS reconfiguration tool [12,13]. IMPRESS is an open-source (https://des-cei.github.io/tools/ impress) design tool developed by the authors targeting the implementation of reconfigurable systems.…”

Section: A New Approach To Build a Scalable Bbnnmentioning

confidence: 99%

“…This strategy reduces the memory footprint and the time required for scaling the network. It is enabled by the advanced reconfiguration capabilities provided by the IMPRESS [12,13] reconfiguration tool. Moreover, advanced fine-grain reconfiguration features are used in the proposed architecture to modify the parameters of the network during evolution, without requiring a global configuration infrastructure reaching each PE.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A Dynamically Reconfigurable BbNN Architecture for Scalable Neuroevolution in Hardware

García¹,

Zamacola²,

Otero³

et al. 2020

Electronics

Self Cite

View full text Add to dashboard Cite

In this paper, a novel hardware architecture for neuroevolution is presented, aiming to enable the continuous adaptation of systems working in dynamic environments, by including the training stage intrinsically in the computing edge. It is based on the block-based neural network model, integrated with an evolutionary algorithm that optimizes the weights and the topology of the network simultaneously. Differently to the state-of-the-art, the proposed implementation makes use of advanced dynamic and partial reconfiguration features to reconfigure the network during evolution and, if required, to adapt its size dynamically. This way, the number of logic resources occupied by the network can be adapted by the evolutionary algorithm to the complexity of the problem, the expected quality of the results, or other performance indicators. The proposed architecture, implemented in a Xilinx Zynq-7020 System-on-a-Chip (SoC) FPGA device, reduces the usage of DSPs and BRAMS while introducing a novel synchronization scheme that controls the latency of the circuit. The proposed neuroevolvable architecture has been integrated with the OpenAI toolkit to show how it can efficiently be applied to control problems, with a variable complexity and dynamic behavior. The versatility of the solution is assessed by also targeting classification problems.

show abstract

Section: Proposed Evolutionary Algorithmmentioning

confidence: 99%

Section: A New Approach To Build a Scalable Bbnnmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A Dynamically Reconfigurable BbNN Architecture for Scalable Neuroevolution in Hardware

García¹,

Zamacola²,

Otero³

et al. 2020

Electronics

Self Cite

View full text Add to dashboard Cite

show abstract

“…This paper provides an integrated vision of multi-grain reconfiguration, showing how coarse, medium, and fine grain reconfiguration can be combined in a given design to leverage each granularity strength. Moreover, we have extended the IMPRESS design automation tool, initially proposed in [11] and [12], with support for design and run-time management of medium grain and fine grain reconfiguration. With IMPRESS, it is now possible to combine all the three granularities in the same system.…”

Section: Introductionmentioning

confidence: 99%

An Integrated Approach and Tool Support for the Design of FPGA-Based Multi-Grain Reconfigurable Systems

et al. 2020

Self Cite

View full text Add to dashboard Cite

Dynamic partial reconfiguration technique can be used to modify regions of an FPGA as large as the whole reconfigurable fabric or as small as individual logic elements. However, FPGA manufacturers have focused their efforts on designing tools that support the design of monolithic reconfigurable accelerators spanning large regions of the device. Nevertheless, in some applications, it is enough to fine-tune the accelerators' behavior instead of changing them entirely. In these cases, rather than allocating new accelerators, it is possible to reconfigure individual logic elements of the circuit, such as look-up tables or flip-flops. There is also an intermediate approach that targets the reconfigurability of accelerators composed of several tightly interconnected modules, such as overlays. In those architectures, it is possible to reconfigure only the modules that differ between the existing accelerator versions, thus reducing the reconfigurable footprint granularity. This paper proposes a classification of the approaches above, categorizing them as coarse, fine, and medium grain, respectively. There are neither commercial nor academic tools supporting multi-grain reconfiguration to take advantage of each granularity strength on commercial FPGAs. Differently, this paper proposes a tool called IMPRESS, that provides design-time and run-time support for multi-grain reconfiguration in Xilinx 7 Series FPGAs. Specific criteria are provided to combine the different granularity levels, trading off the benefits in terms of flexibility and performance, with different design and run-time costs. Two use cases in the image processing and neural network domains have been implemented to show how IMPRESS can build multi-grain reconfigurable systems.

show abstract

Automated Tool and Runtime Support for Fine-Grain Reconfiguration in Highly Flexible Reconfigurable Systems

Cited by 2 publications

References 1 publication

A Dynamically Reconfigurable BbNN Architecture for Scalable Neuroevolution in Hardware

A Dynamically Reconfigurable BbNN Architecture for Scalable Neuroevolution in Hardware

An Integrated Approach and Tool Support for the Design of FPGA-Based Multi-Grain Reconfigurable Systems

Contact Info

Product

Resources

About