Automated Testing Algorithm for the Improvement of 1T1R ReRAM Endurance

Kondratyuk, Ekaterina; Matveyev, Yury; Chouprik, Anastasia; Горнев, Е. С.; Zhuk, Maksim Yu.; Kirtaev, Roman V.; Shadrin, A. V.; Negrov, Dmitrii

doi:10.1109/ted.2021.3105089

Cited by 2 publications

(2 citation statements)

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“…Adaptive write methods, multi-level sensing as well as complementary logic operations in the periphery and parallelization, are some issues to be taken into consideration in the design of the memory read/write drivers, which can require asynchronous circuit techniques. Moreover, designfor-test (DfT) techniques are required [6] to detect undefined state faults (USFs) during memory operation (not covered in this paper). In the context of our case study, Fig.…”

Section: B Ad-hoc Read/write Driver For Logic Operationsmentioning

confidence: 99%

“…It should guarantee a universal logic set and offer flexibility of data movement, required for multi-level (sequential) logic computations. Moreover, device variability is a reliability limiting factor, so its effects must be mitigated at circuit level with proper read/write methodologies that incorporate testability during normal circuit operation [6]. Furthermore, ad-hoc synthesis tools are required to bridge the gap between primitive logic gates and large-scale logic circuits.…”

Section: Introductionmentioning

confidence: 99%

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Circuit Topology and Synthesis Flow Co-Design for the Development of Computational ReRAM

Fernandez

Vourkas

Rubio

2022

2022 IEEE 22nd International Conference on Nanotechnology (NANO)

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Emerging memory technologies will play a decisive role in the quest for more energy-efficient computing systems. Computational ReRAM structures based on resistive switching devices (memristors) have been explored for inmemory computations using the resistance of ReRAM cells for storage and for logic I/O representation. Such approach presents three major challenges: the support for a memristororiented logic style, the ad-hoc design of memory array driving circuitry for memory and logic operations, and the development of dedicated synthesis tools to instruct the multi-level operations required for the execution of an arbitrary logic function in memory. This work contributes towards the development of an automated design flow for ReRAM-based computational memories, highlighting some important HW-SW co-design considerations. We briefly present a case study concerning a synthesis flow for a nonstateful logic style and the co-design of the underlying 1T1R crossbar array driving circuit. The prototype of the synthesis flow is based on the ABC tool and the Z3 solver. It executes fast owing to the level-by-level mapping of logic gates. Moreover, it delivers a mapping that minimizes the logic function latency through parallel logic operations, while also using the less possible ReRAM cells.

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Section: B Ad-hoc Read/write Driver For Logic Operationsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%