Automated TEM Sample Preparation on Wafer Level for Metrology and Process Control

Abstract

As the feature size of semiconductor technology shrinks, cross-section metrology becomes more and more challenging. The generation of cross section metrology data is important for the introduction of new advanced integration schemes, rapid yield learning, and continuous process control for stable manufacturing. In this paper an automated way of TEM cross-section preparation by FIB is described to ensure fast cycle time for preparation and analysis. A dual column FIB/SEM system is used to prepare TEM samples from multiple locations of a 300 mm wafer batch. Subsequently, the TEM lamella is transferred to a grid using an ex-situ lift-out station. Two dedicated applications are shown, a Focus Exposure Matrix (FEM) on patterned photo resist and a process control case study on an etched poly-silicon transistor gate.