Automated synthesis of resilient and tamper-evident analog circuits without a single point of failure

Abstract

This study focuses on the use of genetic programming to automate the design of robust analog circuits. We define two complementary types of failure modes: partial short-circuit and partial disconnect, and demonstrated novel circuits that are resilient across a spectrum of fault levels. In particular, we focus on designs that are uniformly robust, and unlike designs based on redundancy, do not have any single point of failure. We also explore the complementary problem of designing tamper-proof circuits that are highly sensitive to any change or variation in their operating conditions. We find that the number of components remains similar both for robust and standard circuits, suggesting that the robustness does not necessarily come at significant increased circuit complexity. A number of fitness criteria, including surrogate models and co-evolution were used to accelerate the evolutionary process. A variety of circuit types were tested, and the practicality of the generated solutions was verified by physically constructing the circuits and testing their physical robustness.

An incremental evolutionary algorithm suitable for industrial platform for analog circuit design

“…The number of sampling points is P: (9) where the range of the sampling frequency is (M,N)Hz, and (9) is calculated by experimental analysis. With taking the simulation results of controlled precision into the fitness equation (1), the circuit is estimated.…”

“…The majority of evolutionary algorithm they used is Genetic Programming (GP) [4] [8], Genetic Algorithms (GA) [5] [6], Differential Evolution (DE) [2], Evolutionary Strategies (ES) [9] [7]. Some circuit simulators including such simple models as winspice are adopted in the study of automatic analog circuit evolutionary design [6].…”

Open-ended evolution to discover analogue circuits for beyond conventional applications

“…In [14], the set of experiments have proven that the open-ended techniques enable the design of low/high-pass filters with topology-based robustness. In [15], the frequencydiscriminator robust to wide temperature range was evolved with an open-ended GA, intrinsically in FPGA.…”

“…The other approach proposes, at the outset, an evolutionary system targeted at producing robust designs [13,14,17]. In the current study, we adopt the first approach focusing on the exploration of the technique's capabilities to create novel designs, leaving the evolution of robustness for the next stage.…”

“…In the past, low-pass filters [1,14,[18][19][20][21][22][23][24], high-pass filters [1,14,19,21,25,26], amplifiers [15,[18][19][20] and CCs [4][5][6][7] have been successfully synthesised with the help of EA. In [27], spatially and temporally unconstrained evolution was applied to digital reconfigurable hardware-an FPGA.…”