Automated synthesis of asynchronous event-based interfaces for neuromorphic systems

Abstract

Abstract-We present an automated design approach that leverages the commonly available digital design tools in order to rapidly synthesize asynchronous event-based interface circuits from behavioral VHDL code. As part of the proposed design approach, we describe a verification methodology that is able to reveal early in the design process potential timing failures in the generated circuits. Due to the fast design cycle, the approach presented allows designers to quickly explore different architectures for asynchronous circuits and compare them using quantitative metrics based for example on power consumption or silicon area. We validated the proposed design method by synthesizing asynchronous interface circuits for a neuromorphic multi-neuron architecture, and fabricating the VLSI device. We present data from silicon that demonstrates the correct operation of the automatically generated circuits.

A Neuromorphic Event-Based Neural Recording System for Smart Brain-Machine-Interfaces

“…In the case of multiple asynchronous channels producing AEs in parallel, an arbitration block would ensure that these signals do not collide, but are transmitted on the shared bus in sequence. The throughput of multi-node/multi-channel AER systems is typically in the order of 5 megaevents/s [24].…”