Automated optimization of look-up table implementation for function evaluation on FPGAs

Abstract

This paper presents a systematic approach for automatic generation of look-up-table (LUT) for function evaluations and minimization in hardware resource on field programmable gate arrays (FPGAs). The class of functions supported by this approach includes sine, cosine, exponentials, Gaussians, the central B-splines, and certain cylinder functions that are frequently used in applications for signal and image processing and data processing. In order to meet customer requirements in accuracy and speed as well as constraints on the use of area and on-chip memory, the function evaluation is based on numerical approximation with Taylor polynomials. Customized data precisions are supported in both fixed point and floating point representations. The optimization procedure involves a search in three-dimensional design space of data precision, sampling density and approximation degree. It utilizes both model-based estimates and gradient-based information gathered during the search. The approach was tested with actual synthesis results on the Xilinx Virtex-2Pro FPGA platform.

Accelerating the Nonuniform Fast Fourier Transform Using FPGAs

“…We provide support for a variety of kernel functions such as Gaussian, central B-splines, sinc, bessel etc. using LUT-based Taylor polynomial evaluation via Horner's rule as explained in [16]. We provide hardware support for the above technique by implementing a pipeline for the Horner's rule that accepts the degree of Taylor polynomial as a HDL parameter and uses FPGA BRAMs to store LUTs.…”

Asynchronous Device Detection for Cognitive Device-to-Device Communications

“…For the typical sensing-transmission frame length of 20∼100 milliseconds, therefore, the time-delay will be basically negligible. Also, if further considering the resource-efficient automatic generation of look-up-table [47], the power consumption is not really a big cost when implementing the algorithm locally (around 10 times per second in detection stage).…”

Automatic Generation of LUTs for Hardware Neural Networks

“…Other problem in Zhang's work is the dependency of MATLAB software and tools that also can be considered a limitation. Deng et al [12] developed a method to generate LUTs for FPGA implementation. The method approximates the function by a truncate Taylor expansion and then calculates the round-off errors.…”