Automated Full Chip SPICE simulations with self-checking assertions for last mile verification &amp; first pass Silicon of mixed signal SoCs

Harinarayan, Gautham S.; Rana, Manmohan; Pant, Nitin; Bansal, Manish; Sharma, Sarthak; Kaundal, Nishant

doi:10.1109/socc.2016.7905462

Cited by 3 publications

(1 citation statement)

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“…The work of Harinarayana et al [10] presented an automated verification model for mixed-signal SoCs designed for modern application by integrating analog, digital and mixed signals. The verification is performed at different levels and different modes.…”

Section: Introductionmentioning

confidence: 99%

An optimized method towards formal verification of mixed signals using differential fed neural network over FFNN

Vidya¹,

Ramachandra²

2019

IJECE

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<span lang="EN-US">Today, the semiconductor industries are rapidly usinganalog and mixed signals to achieve cost-effective solutions on a System on Chip (SoC) design. The SoC device is a part of analog, digital and essential mixed-signal models/circuits merged on a semiconductor device, which provides the platform to build modern retail/consumer electronics appliances with smart technology. In order to evaluate the mixed signals, the conventional approaches are not effective with respect to its performance, time and manufacturing cost. Thus, the recent researches were much interested in formal verification technique as it provides the evidence of conscious algorithms in a system. The demand for formal verification in the SoC designs in the context of software and hardware platform is high because of its cost and accuracy. Thus, the paper introduces atechnique of formal verification for mixed signals by using training models of the Differential fed neural network (DFNN) over feedforward neural network (FFNN). The formal verification is performed through equivalence checking by using recently adopted designs as reference designs. The outcomes of the verification techniques suggests that DFNN based technique improves the training accuracy and optimizes the hardware resources like area, power than the FFNN based technique.</span>

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Section: Introductionmentioning

confidence: 99%