Automated design flow for no-cost configuration error detection in sram-based FPGAs

Abstract

Soft errors in the configuration memory of SRAMbased FPGAs cause significant and remanent application disturbances. However, classical mitigation techniques based on massive redundancy are too costly for most applications. The method presented in this paper is based on selective redundancy in partially used LUTs. It can be applied so that no hardware is added at the system level and it has been automated in standard design flows for Xilinx and Altera families. The detection of soft errors in the configuration is performed within one clock period. Experimental results on benchmark implementations are discussed, showing the good ratio between coverage and blocklevel overheads, with almost no impact on power and delay. The differences between applying the approach to Virtex V and Stratix IV devices are also discussed.

Parity Waterfall method

“…2) LUT Content Faults: Most methods are based on the dual-output LUTs and use the unused parts of the LUTs to mask some faults in the LUTs by duplication [10], [11], [12] or use TMR method [13]. The method presented in [14] maximizes the fault-masking capabilities of a LUT using logic decomposition and restructuring.…”

“…The method presented in [12] uses similar technique to the one presented in this paper, but it is based on duplication, thus it requires comparators to operate and it is not focused to achieve 100% fault coverage. Our proposed parity waterfall method combines several practices, it is able to cover all possible faults and uses the basic element of existing modern FPGAs.…”