Attacks and Countermeasures for Capacitive PUF-Based Security Enclosures

Garb, Kathrin; Schink, Marc; Hiller, Matthias; Obermaier, Johannes

doi:10.1109/paine54418.2021.9707704

Cited by 2 publications

(2 citation statements)

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“…(ii) During runtime of the device, he can drill a hole into the envelope and try to gain access to the sensitive data in a minimally invasive way to prevent zeroization. An investigation of micro-drilling attacks, magnetic probing, and bypassing of electrodes was published by Garb et al [GSHO21] in the context of the capacitive PUF-based enclosure, including countermeasures. The enclosure was designed [ION + 19, IOK + 18] to withstand 250-300 µm diameter drilling attacks that can be reliably detected.…”

Section: The Wiretap Channel and Attacker Modelmentioning

confidence: 99%

The Wiretap Channel for Capacitive PUF-Based Security Enclosures

Garb

Xhemrishi

Kürzinger

et al. 2022

TCHES

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In order to protect devices from physical manipulations, protective security enclosures were developed. However, these battery-backed solutions come with a reduced lifetime, and have to be actively and continuously monitored.In order to overcome these drawbacks, batteryless capacitive enclosures based on Physical Unclonable Functions (PUFs) have been developed that generate a keyencryption-key (KEK) for decryption of the key chain. In order to reproduce the PUF-key reliably and to compensate the effect of noise and environmental influences, the key generation includes error correction codes. However, drilling attacks that aim at partially destroying the enclosure also alter the PUF-response and are subjected to the same error correction procedures. Correcting attack effects, however, is highly undesirable as it would destroy the security concept of the enclosure. In general, designing error correction codes such that they provide tamper-sensitivity to attacks, while still correcting noise and environmental effects is a challenging task.We tackle this problem by first analyzing the behavior of the PUF-response under external influences and different post-processing parameters. From this, we derive a system model of the PUF-based enclosure, and construct a wiretap channel implementation from q-ary polar codes. We verify the obtained error correction scheme in a Monte Carlo simulation and demonstrate that our wiretap channel implementation achieves a physical layer security of 100 bits for 306 bits of entropy for the PUF-secret. Through this, we further develop capacitive PUF-based security enclosures and bring them one step closer to their commercial deployment.

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Section: The Wiretap Channel and Attacker Modelmentioning

confidence: 99%

The Wiretap Channel for Capacitive PUF-Based Security Enclosures

Garb

Xhemrishi

Kürzinger

et al. 2022

TCHES

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“…Estimating the inter-distance requires extensive measurements on a large number of boards, which was beyond the scope of this work. If the inter-distance requirements are met, then it is also conceivable to apply PUF key derivation techniques proposed in [IU19,GXKF22] to extract high-entropy keys from PDN impedance measurements.…”

Section: Impedanceverif As Puf?mentioning

confidence: 99%

ImpedanceVerif: On-Chip Impedance Sensing for System-Level Tampering Detection

Mosavirik

Schaumont

Tajik

2022

TCHES

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Physical attacks can compromise the security of cryptographic devices. Depending on the attack’s requirements, adversaries might need to (i) place probes in the proximity of the integrated circuits (ICs) package, (ii) create physical connections between their probes/wires and the system’s PCB, or (iii) physically tamper with the PCB’s components, chip’s package, or substitute the entire PCB to prepare the device for the attack. While tamper-proof enclosures prevent and detect physical access to the system, their high manufacturing cost and incompatibility with legacy systems make them unattractive for many low-cost scenarios. In this paper, inspired by methods known from the field of power integrity analysis, we demonstrate how the impedance characterization of the system’s power distribution network (PDN) using on-chip circuit-based network analyzers can detect various classes of tamper events. We explain how these embedded network analyzers, without any modifications to the system, can be deployed on FPGAs to extract the frequency response of the PDN. The analysis of these frequency responses reveals different classes of tamper events from board to chip level. To validate our claims, we run an embedded network analyzer on FPGAs of a family of commercial development kits and perform extensive measurements for various classes of PCB and IC package tampering required for conducting different side-channel or fault attacks. Using the Wasserstein Distance as a statistical metric, we further show that we can confidently detect tamper events. Our results, interestingly, show that even environment-level tampering activities, such as the proximity of contactless EM probes to the IC package or slightly polished IC package, can be detected using on-chip impedance sensing.

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Attacks and Countermeasures for Capacitive PUF-Based Security Enclosures

Cited by 2 publications

References 0 publications

The Wiretap Channel for Capacitive PUF-Based Security Enclosures

The Wiretap Channel for Capacitive PUF-Based Security Enclosures

ImpedanceVerif: On-Chip Impedance Sensing for System-Level Tampering Detection

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