ATPG for timing-induced functional errors on trigger events in hardware-software systems

Abstract

We consider timing-induced functional errors in inter process communication. We present an A utomatic Test Pattern Generation (ATPG) algorithm for the co-validation of hardware-software systems. Events on trigger signals ( signals contained in the sensitivity list of a process) implement the basic synchronization mechanism in most hardware-software description languages. Timing faults on trigger signals can have a serious impact on system behavior. We target timing faults on trigger signals by enhancing a timing fault model proposed in previous work. The ATPG algorithm which we present targets the new timing fault model and provides significant performance benefits over manual test generation which is typically used for co-validation.

Efficient Methodology for ISO26262 Functional Safety Verification

“…To address this challenge, we can deploy different verification technologies in a single methodology. Methodologies applying Formal Methods to identify faults that cannot propagate to outputs of the design (Safe faults) [4][5] [6], and ATPG techniques to generate test patterns that potentialize fault propagation [7] [8] have been proposed. Even though Simulation, Formal Methods and ATPG have complementary strengths, to the best of our knowledge, they were not previously combined in a single fault analysis flow that aims at fault propagation for compliance to ISO26262 requirements.…”

Combining Fault Analysis Technologies for ISO26262 Functional Safety Verification

“…ATPG tools are able to create test patterns that potentialize fault propagation. Simulation can be performed with the generated test vectors aiming to achieve better failure coverage with reduced simulation times [8] [9]. Nonetheless, ATPG focuses on manufacturing test and is not optimal for determining untestable faults or covering faults on areas out of the scan chains reach.…”