Atomistic Pseudo-Transient BTI Simulation With Inherent Workload Memory

Abstract

Bias Temperature Instability (BTI) is a major concern for the reliability of decameter to nanometer devices. Older modeling approaches fail to capture time-dependent device variability or maintain a crude view of the device's stress. Previously, a two-state atomistic model has been introduced, which is based on gate stack defect kinetics. Its complexity has been preventing seamless integration in simulations of large device inventories over typical system lifetimes. In this paper, we present an approach that alleviates this complexity. We introduce a novel signal representation for the gate stress. Using this format, atomistic BTI simulations require less model iterations while exhibiting minimum accuracy degradation. We also enable full temperature and voltage supply dependency since these attributes are far from constant in modern integrated systems. The proposed simulation methodology retains both the atomistic property and the workload memory that remain major differentiators of defect-based BTI simulation, in comparison to state-of-the-art approaches.

Impact and mitigation of SRAM read path aging

“…Menchaca et al [8] analyzed the BTI impact on different sense amplifier designs implemented on 32 nm technology node by using failure probability (i.e., flipping a wrong value) as a reliability metric. Agbo et al [9,10,11,12,13,14,15,16] investigated the BTI impact on SRAM drain-input and standard latch-type sense amplifier design, while considering process, supply voltage, and temperature (PVT) variations in the presence of varying workloads and technology nodes. Other research focused on mitigation schemes.…”