Atomic Layer Etching: What Can We Learn from Atomic Layer Deposition?

Faraz, Tahsin; Roozeboom, F.; Knoops, Hcm Harm; Kessels, Wmm Erwin

doi:10.1149/2.0051506jss

Cited by 126 publications

(115 citation statements)

References 73 publications

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“…10,15 In this case one may need less directional etch conditions, and higher pressures in combination with dedicated microplasma sources may accomplish this. In the next section we will discuss the general trends in microplasma source design and miniaturization.…”

Section: Timescale Analysis For Convection Diffusion Deposition Andmentioning

confidence: 99%

“…15 We suffice by resuming the main distinction of ALEt from conventional plasma etching: ideally, ALEt removes only one atomic (sub)layer from the parent material per basic adsorptionpurge-activation-purge cycle. In conventional etching, even with fast (i.e.…”

mentioning

confidence: 99%

“…Other remarkable similarities between ALD and ALEt both in full and selective area processing. 15 3. The similarity between time-multiplexed etch/sidewall passivation sequencing in (D)RIE and the sequencing of precursor(s) and co-reactant(s) in ALD and ALEt, and also the duration of these cycle times (∼a few seconds).…”

mentioning

confidence: 99%

“…38,39 Interestingly, and seemingly controversial, this also includes the need for tunable plasma process parameters to initiate isotropic desorption from and volatilization of the surface independent of its local orientation. 10,15 11. The development of dedicated (micro)plasma sources in general 40 and atmospheric pressure sources in particular to increase throughput, deposition rate and to reduce process temperature and gas consumption.…”

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confidence: 99%

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Cyclic Etch/Passivation-Deposition as an All-Spatial Concept toward High-Rate Room Temperature Atomic Layer Etching

Roozeboom

Bruele

Creyghton

et al. 2015

ECS J. Solid State Sci. Technol.

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Conventional (3D) etching in silicon is often based on the 'Bosch' plasma etch with alternating half-cycles of a directional Sietch and a fluorocarbon polymer passivation. Also shallow feature etching is often based on cycled processing. Likewise, ALD is time-multiplexed, with the extra benefit of half-reactions being self-limiting, thus enabling layer-by-layer growth in a cyclic process. To speed up growth rate, spatial ALD has been successfully commercialized for large-scale and high-rate deposition at atmospheric pressure. We conceived a similar spatially-divided etch concept for (high-rate) Atomic Layer Etching (ALEt). The process is converted from time-divided into spatially-divided by inserting inert gas-bearing 'curtains' that confine the reactive gases to individual injection slots in a gas injector head. By reciprocating substrates back and forth under such head one can realize the alternate etching/passivation-deposition cycles at optimized local pressures, without idle times needed for switching pressure or purging. Another improvement toward an all-spatial approach is the use of ALD-based oxide (Al 2 O 3 , SiO 2 , etc.) as passivation during, or gap-fill after etching. This approach, called spatial ALD-enabled RIE, has industrial potential in cost-effective back-endof-line and front-end-of-line processing, especially in patterning structures requiring minimum interface, line edge and fin sidewall roughness (i.e., atomic-scale fidelity with selective removal of atoms and retention of sharp corners). Today, the continuous doubling of the transistor count on planar microprocessor and memory chips in a two-year cadence has reached the point where Moore's Law (essentially an economic law) and Dennard's scaling (transistor and pitch dimensions) have approached their limits in 2D-scaling. The end of the planar device era was marked with the introduction in 2011 of the 22-nm Tri-Gate device.1,2 Figure 1 shows its design with gates surrounding the channel on three sides of vertical fins to improve gate delay.Today, at the emergence of the 10-nm technology node and the 50 th anniversary of Moore's Law, 3D device and integration solutions are being rapidly introduced both intra-chip, e.g., Gate-All-Around, 3 vertical NAND, 4 and inter-chip, e.g., 3D Through-Silicon Vias (TSVs). 5History of 3D etching.-Whereas the transistor design has been planar for most of its history, its periphery has been subjected to 3D design early on. One of the earliest 3D concepts has been the basic invention of 3D TSVs, already filed in 1958 by the famous W. Shockley, 6 cf. Fig. 2. Yet, in reality 3D Through-Silicon Via (TSV) technology took decades to accelerate the now rapidly growing stacked-chips and micro-electromechanical systems (MEMS) markets by enabling their interconnection in a 3D-integrated System-in-Package (i.e. the so-called 'More than Moore' domain). Today, the mainstream industrial technology for etching of both TSV and MEMS structures is ion-assisted etching or (Deep) Reactive Ion Etching. This method has become so ...

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Section: Timescale Analysis For Convection Diffusion Deposition Andmentioning

confidence: 99%

mentioning

confidence: 99%

mentioning

confidence: 99%

mentioning

confidence: 99%

See 2 more Smart Citations

Cyclic Etch/Passivation-Deposition as an All-Spatial Concept toward High-Rate Room Temperature Atomic Layer Etching

Roozeboom

Bruele

Creyghton

et al. 2015

ECS J. Solid State Sci. Technol.

Self Cite

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“…This recently triggered industrial interest in atomic layer etching (ALE) of traditional semiconductors. [1][2][3] ALE is a cyclic thin film etching process that uses self-limiting reactions, 4,5 in order to obtain a well defined etch per cycle. This can be a single atomic (or molecular, as in this work) layer etched in one etch cycle.…”

mentioning

confidence: 99%

Atomic layer etching of gallium nitride (0001)

Kauppinen

Khan

Sundqvist

et al. 2017

Journal of Vacuum Science &Amp; Technology A: Vacuum, Surfaces, and Films

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In this work, atomic layer etching (ALE) of thin film Ga-polar GaN(0001) is reported in detail using sequential surface modification by Cl2 adsorption and removal of the modified surface layer by low energy Ar plasma exposure in a standard reactive ion etching system. The feasibility and reproducibility of the process are demonstrated by patterning GaN(0001) films by the ALE process using photoresist as an etch mask. The demonstrated ALE is deemed to be useful for the fabrication of nanoscale structures and high electron mobility transistors and expected to be adoptable for ALE of other materials

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Etching of Semiconductor Devices

Lill

Vahedi

Gottscho

2019

Materials Science and Technology

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Plasma etching or reactive ion etching (RIE) has been the workhorse for patterning of semiconductor devices since the early 1980s when it replaced wet etching in manufacturing. Today, RIE is reaching levels of performance that were unimaginable back then. At the same time, etching technologies such as atomic layer etching (ALE), radical dry vapor etching, and ion beam etching are finding their way into manufacturing for certain applications. Herein, we present an overview of dry etching technologies used in semiconductor manufacturing. The emphasis is on the elementary surface processes and how they impact the performance on the wafer. We will start from less complex etching technologies, which use just one kind of etching species, such as neutrals, radicals, or ions. Then we combine these techniques into cycling processes, which leads to the discussion of ALE. The highest level of complexity is reached in RIE with simultaneous species fluxes. Reactor designs for the various etching technologies and process control will be covered. Finally, the outlook into the future of semiconductor device etching will be given.

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Atomic Layer Etching: What Can We Learn from Atomic Layer Deposition?

Cited by 126 publications

References 73 publications

Cyclic Etch/Passivation-Deposition as an All-Spatial Concept toward High-Rate Room Temperature Atomic Layer Etching

Cyclic Etch/Passivation-Deposition as an All-Spatial Concept toward High-Rate Room Temperature Atomic Layer Etching

Atomic layer etching of gallium nitride (0001)

Etching of Semiconductor Devices

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