Atomic-layer-deposited LaAlO<inf>3</inf>/SrTiO<inf>3</inf> all oxide field-effect transistors

Abstract

We have demonstrated well-behaved accumulation-mode all oxide NMOSFETs with amorphous atomic-layer-deposited (ALD) LaAlO 3 gate dielectric stacks on crystalline SrTiO 3 substrates. A maximum drain current exceeding 10 mA/mm has been obtained on a 3.75μm-gate-length device, proving a very conductive channel can be formed at the oxide-oxide interface. Four different gate dielectric stacks, which are Lafirst cycle LaAlO 3 , Al-first cycle LaAlO 3 , LaAlO 3 with 1.5 nm La 2 O 3 interfacial layer, and LaAlO 3 with 1.8 nm Al 2 O 3 interfacial layer, have been deposited on SrTiO 3 substrates to systematically study their effects on the conductivity at the different oxide-oxide interfaces. The experimental results show that a La-initiated interfacial layer is preferable to form a more conducting channel at the LaAlO 3 /SrTiO 3 interface. Low temperature characteristics have also been utilized to provide an in-depth understanding of the channel formation at the oxideoxide interface. The availability of the MBE technology to epitaxially grow SrTiO 3 on Si substrate provides the pathway to integrate ALD LaAlO 3 /SrTiO 3 devices on Si platform.

Field-Effect Device Using Quasi-Two-Dimensional Electron Gas in Mass-Producible Atomic-Layer-Deposited Al2O3/TiO2 Ultrathin (<10 nm) Film Heterostructures

“…Dong et al and Forg et al have reported the I on of ∼9 μA/μm with an I on /I off ratio of ∼10 3 and an I on /I off ratio of ∼10 4 with an I on of ∼0.015 μA/ μm, respectively, from oxide heterostructure devices using a single-crystalline STO substrate. 26,27 The high I on /I off ratio (∼10 8 ) of FET using an Al 2 O 3 /TiO 2 heterojunction originates from an extremely low I off value of ∼10 −8 μA/μm via facile carrier depletion at both the interface and the entire TiO 2 bottom layer due to its extreme thinness (<∼7 nm). For a thick bottom layer such as the STO single crystal (∼0.5 mm thick) in LAO/STO heterostructures, electrons dissipated from 2DEG channel at the interface but not depleted in the thick STO layer induce the bulk leakage path under the interface (2DEG channel) to contribute to I off .…”

Physics of SrTiO3-based heterostructures and nanostructures: a review

“…Also, each precursor must be flushed from the growth chamber before the next precursor can be introduced. With ALD and suitable precursors, various SrTiO 3 -based heterostructures have been reported, from SrTiO 3 film on Ru and TiO 2 -colated Ru [270], amorphous LaAlO 3 /SrTiO 3 [223,271], LaAlO 3 /SrTiO 3 [272], (partially amorphous) LaAlO 3 /SrTiO 3 on SrTiO 3 -buffered Si (001) [273].…”

Schottky barrier diode based on β-Ga2O3 (100) single crystal substrate and its temperature-dependent electrical characteristics

“…In the design of the Schottky barrier diode, the Ti and Pt metals were selected, respectively, to act the ohmic and Schottky electrodes to construct the Pt/ b-Ga 2 O 3 /Ti structure (as shown in the inset of Figure 2(a)). After chemically cleaning the Ga 2 O 3 wafer with organic solvent (acetone and methanol) and ultra pure water, the surface of the back side was etched with inductively coupled plasma (ICP) technique using a BCl 3 gas with a flow of 20 sccm for 80 s under the plasma/bias power of 400 W/30 W. The etching might increase the back side roughness (reaching 2 nm in our sample) and generate large-density surface defects such as oxygen vacancies that act as donors, 13,25,26 so the ohmic contact can be enhanced and the contact resistance with Ti can be decreased. Then two sequential layers of Ti/Au with the thickness of 10/230 nm, respectively, were deposited on the back side of the substrate via magnetron sputtering to act as cathode.…”