Atomic Layer Deposited Al<sub>2</sub>O<sub>3</sub> Encapsulation for the Silicon Interconnect Fabric

Chase, Niloofar Shakoorzadeh; Sahoo, Krutikesh; Yang, Yu Tao; Iyer, Subramanian S.

doi:10.1109/ectc32862.2020.00198

Cited by 5 publications

(3 citation statements)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Chase et al have successfully demonstrated that an Al 2 O 3 barrier at thicknesses from 10 to 17 nm can block copper oxide formation for up to 216 h of stress testing. 14 However, their process is performed at 200 °C which is generally the upper limit for most polymers. In this work, the RDLs are Cu lines surrounded by a thermoset phenol-based photosensitive polymer.…”

mentioning

confidence: 99%

“…This condition excludes many relevant materials like TaN, Mn, and Ru, which are popular barrier layer and liner materials in interconnects, as they can only be deposited at higher processing temperatures. Chase et al have successfully demonstrated that an Al 2 O 3 barrier at thicknesses from 10 to 17 nm can block copper oxide formation for up to 216 h of stress testing . However, their process is performed at 200 °C which is generally the upper limit for most polymers.…”

mentioning

confidence: 99%

See 1 more Smart Citation

Investigating the Efficacy of Hafnium Dioxide Barrier Layers to Halt Copper Oxide Formation in Redistribution Layers for Three-Dimensional (3D) Packaging

Chery

Armini

2022

J. Phys. Chem. Lett.

View full text Add to dashboard Cite

mentioning

confidence: 99%

mentioning

confidence: 99%

Investigating the Efficacy of Hafnium Dioxide Barrier Layers to Halt Copper Oxide Formation in Redistribution Layers for Three-Dimensional (3D) Packaging

Chery

Armini

2022

J. Phys. Chem. Lett.

View full text Add to dashboard Cite

“…[4][5][6][7] Also, during device operation, encapsulation is needed around the metal. 8,9 (3) The throughput of TCB is modest for die-to-wafer (D2W) bonding because of the time needed for temperatures to ramp up and down. (4) Finally, since the temperature of the alignment and bonding process is high, the thermal expansion in optics degrades the alignment and overlay, preventing interconnection pitch from scaling down to finer pitch.…”

mentioning

confidence: 99%

Mechanism and Process Window Study for Die-to-Wafer (D2W) Hybrid Bonding

Ren

Yang

Ouyang

et al. 2021

ECS J. Solid State Sci. Technol.

Self Cite

View full text Add to dashboard Cite

Room temperature hybrid bonding is a good candidate to replace thermal compression bonding due to its better resistance to Cu oxidation and its capability for large die integration. However, the bonding mechanism with Cu thickness non-uniformity and real dishing conditions has not yet been fully understood. To study the mechanism and to explore the window of annealing temperature for the void-free interface, finite element analysis (FEA) and auxiliary experiments with real process issues have been conducted. A Cu thickness variation of 6.6% across the whole wafer after electroplating causes a metal dishing between 4 and 16 nm during chemical mechanical planarization. The critical stress (78.1 MPa) of dielectric material gives the upper boundary of temperature, and the complete contact of metal limits the lower boundary for our FEA models. The window for the annealing temperature is then simulated to be within a range between 295 °C and 302 °C. This is the first time that FEA with a non-uniform process input has been implemented to generate a process window of die-to-wafer (D2W) hybrid bonding for real world application. This paper provides a deep understanding and practical guidance for D2W hybrid bonding.

show abstract