2021
DOI: 10.1016/j.ceramint.2021.03.249
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Atomic layer chemical vapor deposition of SiO2 thin films using a chlorine-free silicon precursor for 3D NAND applications

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Cited by 11 publications
(5 citation statements)
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“…The realization of a microfabrication process for the construction of high-aspect-ratio micro/nanoscale structures on SiO 2 has been a long-standing goal for the development of novel devices in nanotechnology. The “Bosch process”a deep microfabrication method for Si invented by Robert Bosch GmbH in 1992is widely used to fabricate advanced Si-based devices such as micro-electromechanical systems , and through-silicon vias. , In contrast to pure Si, SiO 2 exhibits high chemical resistance, high transparency in the visible range, low thermal conductivity, and extremely low dielectric loss at high frequencies. , By exploiting these unique characteristics, various SiO 2 -based devices that require vertical microstructures with smooth sidewalls have been developed in recent years, including microfluidic chips , and optical meta-surfaces. , Anisotropic microstructures on SiO 2 are typically fabricated via inductively coupled plasma reactive ion etching (ICP-RIE). However, the fabrication of high-aspect-ratio vertical and smooth-sidewall microstructures has not been achieved using this method because hard mask materials are etched via ion irradiation from an ICP source.…”
Section: Introductionmentioning
confidence: 99%
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“…The realization of a microfabrication process for the construction of high-aspect-ratio micro/nanoscale structures on SiO 2 has been a long-standing goal for the development of novel devices in nanotechnology. The “Bosch process”a deep microfabrication method for Si invented by Robert Bosch GmbH in 1992is widely used to fabricate advanced Si-based devices such as micro-electromechanical systems , and through-silicon vias. , In contrast to pure Si, SiO 2 exhibits high chemical resistance, high transparency in the visible range, low thermal conductivity, and extremely low dielectric loss at high frequencies. , By exploiting these unique characteristics, various SiO 2 -based devices that require vertical microstructures with smooth sidewalls have been developed in recent years, including microfluidic chips , and optical meta-surfaces. , Anisotropic microstructures on SiO 2 are typically fabricated via inductively coupled plasma reactive ion etching (ICP-RIE). However, the fabrication of high-aspect-ratio vertical and smooth-sidewall microstructures has not been achieved using this method because hard mask materials are etched via ion irradiation from an ICP source.…”
Section: Introductionmentioning
confidence: 99%
“… 4 , 5 In contrast to pure Si, SiO 2 exhibits high chemical resistance, high transparency in the visible range, low thermal conductivity, and extremely low dielectric loss at high frequencies. 6 , 7 By exploiting these unique characteristics, various SiO 2 -based devices that require vertical microstructures with smooth sidewalls have been developed in recent years, including microfluidic chips 8 , 9 and optical meta-surfaces. 10 , 11 Anisotropic microstructures on SiO 2 are typically fabricated via inductively coupled plasma reactive ion etching (ICP-RIE).…”
Section: Introductionmentioning
confidence: 99%
“…In general, a-IGZO TFTs are typically fabricated at a process temperature below 400 °C, and there have been reports indicating the possibility of fabricating them even at room temperature . However, the fabrication temperature required for dynamic random-access memory (DRAM) or NAND flash memory exceeds 600 °C, which may pose a significant challenge to the stability and performance of the a-IGZO channel. , The crystallization of sputter-derived a-IGZO after high-temperature annealing has been reported to degrade device performance and stability. , In addition, several reports have pointed out that the desorption of hydrogen (H) species results in the formation of intrinsic defects in the active layer bulk, leading to the degradation of device stability. , Furthermore, defect formation at the active layer/GI interface is accelerated by high-temperature annealing as the interface between the two materials is thermodynamically unstable. , Therefore, it is important to ensure that a-IGZO TFTs fabricated via ALD exhibit high performance and reliability even under high-temperature treatments.…”
Section: Introductionmentioning
confidence: 99%
“…11 However, the fabrication temperature required for dynamic random-access memory (DRAM) or NAND flash memory exceeds 600 °C, which may pose a significant challenge to the stability and performance of the a-IGZO channel. 12,13 The crystallization of sputter-derived a-IGZO after high-temperature annealing has been reported to degrade device performance and stability. 14,15 In addition, several reports have pointed out that the desorption of hydrogen (H) species results in the formation of intrinsic defects in the active layer bulk, leading to the degradation of device stability.…”
Section: Introductionmentioning
confidence: 99%
“…Moreover, SiO 2 is used as a dielectric material in microelectronic circuits. Several techniques have been used to deposit TiO 2 and SiO 2 thin films, including chemical vapor deposition (CVD) [ 7 , 8 ], molecular beam epitaxy [ 9 , 10 ], plasma-enhanced chemical vapor deposition [ 11 , 12 ], the sol–gel process [ 13 , 14 ], and pulsed laser deposition (PLD) [ 15 , 16 ], etc. PLD is a physical vapor deposition technique that uses high-energy laser pulses to ablate the target’s material to obtain, via vapor condensation on a substrate, thin films with excellent structural and optical properties.…”
Section: Introductionmentioning
confidence: 99%