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Srivastava, Amitabh; Eustace, Alan

doi:10.1145/178243.178260

Cited by 606 publications

(16 citation statements)

References 4 publications

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“…To compare these algorithms, we implemented both, as well as some variants, and used the ATOM tool [28] to measure the number of processor cycles spent in computing an optimal path [19]. We ran a series of tests on a multicalendar granularity graph similar to that shown in Fig.…”

Section: Choosing the Methodsmentioning

confidence: 99%

Efficiently supporting temporal granularities

Dyreson

Evans

Lin

et al. 2000

IEEE Trans. Knowl. Data Eng.

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AbstractÐGranularity is an integral feature of temporal data. For instance, a person's age is commonly given to the granularity of years and the time of their next airline flight to the granularity of minutes. A granularity creates a discrete image, in terms of granules, of a (possibly continuous) time-line. We present a formal model for granularity in temporal operations that is integrated with temporal indeterminacy, or ªdon't know whenº information. We also minimally extend the syntax and semantics of SQL-92 to support mixed granularities. This support rests on two operations, scale and cast, that move times between granularities, e.g., from days to months. We demonstrate that our solution is practical by showing how granularities can be specified in a modular fashion, and by outlining a time-and space-efficient implementation. The implementation uses several optimization strategies to mitigate the expense of accommodating multiple granularities.

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Section: Choosing the Methodsmentioning

confidence: 99%

Efficiently supporting temporal granularities

Dyreson

Evans

Lin

et al. 2000

IEEE Trans. Knowl. Data Eng.

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“…First, static methods incur compilation or modification overhead at the time they are applied, which can be large in some tools. For example, while ATOM took less than 10 seconds in most cases to instrument each of the SPEC92 benchmark suite on even old systems like Digital Alpha AXP 3000 Model, the AspectJ 1.1 compiler has been reported to slow down the compilation step by almost 5 times compared to the javac 1.4 reference compiler for inserting 10 different logging aspect codes . Second, there is a runtime overhead in intercepting existing function calls and handling the control of the intercepted calls.…”

Section: Issues In Fci Techniquesmentioning

confidence: 99%

Function call interception techniques

Kang¹

2017

Softw Pract Exp

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Function call interception (FCI), or method call interception (MCI) in the object-oriented programming domain, is a technique of intercepting function calls at program runtime. Without directly modifying the original code, FCI enables to undertake certain operations before and/or after the called function or even to replace the intercepted call. Thanks to this capability, FCI has been typically used to profile programs, where functions of interest are dynamically intercepted by instrumentation code so that the execution control is transferred to an external module that performs execution time measurement or logging operations. In addition, FCI allows for manipulating the runtime behavior of program components at the fine-grained function level, which can be useful in changing an application's original behavior at runtime to meet certain execution requirements such as maintaining performance characteristics for different input problem sets. Due to this capability, however, some FCI techniques can be used as a basis of many security exploits for vulnerable systems. In this paper, we survey a variety of FCI techniques and tools along with their applications to diverse areas in the computing and software domains. We describe static and dynamic FCI techniques at large and discuss the strengths and weaknesses of different implementations in this category. In addition, we also discuss aspect-oriented programming implementation techniques for intercepting method calls.

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“…The programs were generated with the Compaq f77 compiler, applying full optimizations, for an AlphaStation 600 5/266. The traces were obtained by instrumenting the binaries with the ATOM tool [33]. Since the simulator is very slow, due to the detail of the simulations, we run only a portion of 100 M (million) instructions of each benchmark, after skipping an initial start-up phase.…”

Section: Experimental Frameworkmentioning

confidence: 99%

Improving latency tolerance of multithreading through decoupling

Parcerisa

González

2001

IEEE Trans. Comput.

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AbstractÐThe increasing hardware complexity of dynamically scheduled superscalar processors may compromise the scalability of this organization to make an efficient use of future increases in transistor budget. SMT processors, designed over a superscalar core, are therefore directly concerned by this problem. This work presents and evaluates a novel processor microarchitecture which combines two paradigms: simultaneous multithreading and access/execute decoupling. Since its decoupled units issue instructions inorder, this architecture is significantly less complex, in terms of critical path delays, than a centralized out-of-order design, and it is more effective for future growth in issue-width and clock speed. We investigate how both techniques complement each other. Since decoupling features an excellent memory latency hiding efficiency, the large amount of parallelism exploited by multithreading may be used to hide the latency of functional units and keep them fully utilized. Our study shows that, by adding decoupling to a multithreaded architecture, fewer threads are needed to achieve maximum throughput. Therefore, in addition to the obvious hardware complexity reduction, it places lower demands on the memory system. Since one of the problems of multithreading is the degradation of the memory system performance, both in terms of miss latency and bandwidth requirements, this improvement becomes critical for high miss latencies, where bandwidth might become a bottleneck. Finally, although it may seem rather surprising, our study reveals that multithreading by itself exhibits little memory latency tolerance. Our results suggest that most of the latency hiding effectiveness of SMT architectures comes from the dynamic scheduling. On the other hand, decoupling is very effective at hiding memory latency. An increase in the cache miss penalty from 1 to 32 cycles reduces the performance of a 4-context multithreaded decoupled processor by less than 2 percent. For the nondecoupled multithreaded processor, the loss of performance is about 23 percent.

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Cited by 606 publications

References 4 publications

Efficiently supporting temporal granularities

Efficiently supporting temporal granularities

Function call interception techniques

Improving latency tolerance of multithreading through decoupling

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