ATM in B-ISDN communication systems and VLSI realization

Koinuma, T.; Miyaho, Noriharu

doi:10.1109/4.375951

Cited by 16 publications

(3 citation statements)

References 5 publications

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“…Especially in applications such as data communications between processor elements in a parallel computer system and asynchronous transfer mode (ATM) dataexchanges in a public communications backbone network, it will become necessary to handle data bandwidths in excess of 1 Tb/s [2]. However, it is said that semiconductor switches cannot cope with this demand because of increasing difficulties in packaging and power dissipation of LSI chips.…”

Section: Introductionmentioning

confidence: 99%

A 4 X 4 superconducting Batcher-Banyan switch

Hosoya

Kominami²

1997

IEEE Trans. Appl. Supercond.

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The paper describes a Batcher sorter and a Banyan network which together form a nonblocking and self-routing switch. The Batcher sorter sorts input packets in the order of their address values. This sorting operation guarantees no blocking in the succeeding Banyan network and presents an efficient way to check contention. The Banyan network distributes contention-free packets to their final destinations. The Batcher and Banyan switches were designed by using a three-junction SQUID gate family driven by three-phase powering clocks.The Batcher sorter is composed of 2 2 2 Batcher switching elements. Each Batcher switching element sorts two input packets in the order of their address values. A 4 2 4 Batcher sorter with 2-b data width, which is composed of six 2 2 2 Batcher switching elements, was fabricated by an Nb tri-layer process. Its correct operation was confirmed.The Banyan network consists of 2 2 2 Banyan switching elements. A 2 2 2 Banyan switching element with 2-b data width was also fabricated. The correct operation was confirmed up to 4 GHz by using a test pattern generator integrated on-chip.

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Section: Introductionmentioning

confidence: 99%

A 4 X 4 superconducting Batcher-Banyan switch

Hosoya

Kominami²

1997

IEEE Trans. Appl. Supercond.

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“…One of the solutions may be parallel processing with multibit semiconductor switches. However, it is said that this approach will be limited in the near future because of the problems of packaging or power dissipation of huge numbers of semiconductor large scale integrators (LSI's) [4]. Thus, substitute devices using superconducting or optical technologies are now attracting attention [5]- [7].…”

Section: Introductionmentioning

confidence: 99%

3.5 GHz operation of a superconducting packet switch element

Hosoya

Hioe

Kominami

et al. 1996

IEEE Trans. Appl. Supercond.

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The paper introduces a prototype model of a superconducting packet switch which is composed of an input buffer, a contention solver, and a distribution network. The input buffer and the contention solver enable contention-free distribution of data packets. The total design of the prototype has been completed and the total operation has been numerically simulated and confirmed.A 2 2 2 switching element which controls the paths of two packets is the key component of the prototype. The basic switching element with 1-b data-width is fabricated by standard Nb trilayer process. Three-junction SQUID's driven by a three-phase powering clock are used in the switch. The correct operation up to 3.5 GHz, limited by the measurement setup, is confirmed. The margin evaluation shows there remains enough margin at GHz operations.

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“…An asynchronous transfer mode (ATM) is a key technology for multimedia telecommunication networks. The rapid increase in telecommunication traffic demands large throughput over 1 Tbit/s for ATM switching systems by 2010 [1]. The maximum switching capacity reported to date for LSI-based ATM switching systems is 160 Gbit/s [2].…”

Section: Introductionmentioning

confidence: 99%

Clock-frequency and temperature margins of a high-temperature superconductor delay-line memory

Tahara¹

1999

Supercond. Sci. Technol.

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We have developed a 10 GHz 32-bit delay-line memory, using a semiconductor crossbar switch and a YBa2Cu3O7- coplanar delay line. For use in the high-speed (10 GHz) cell-buffer storage of large-throughput (1 Tbit/s) asynchronous transfer mode (ATM) switching systems, this memory must be fairly reliable. To evaluate the reliability of the operation, therefore, we measured the clock-frequency and temperature margins and the temperature dependence of the bit-error rate. At 64 K, this memory has a capacity of 32 bits with a clock frequency of 9.89±0.11 GHz. In general, clock frequencies of communication systems are strictly managed so that the margins are less than 10-6. Therefore, the frequency margin of this memory (~2 × 10-2) is wide enough for use in communication systems. The temperature margin was 71.5±4.3 K at 10 GHz and 33 bits. This memory offered error-free operation (BER < 10-13) at 71.5±3.5 K. These temperature margins are wide enough to be controlled by a cryocooler. These results show that the memory offers reliability and that it can be applied to high-speed ATM cell-buffer storage.

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ATM in B-ISDN communication systems and VLSI realization

Cited by 16 publications

References 5 publications

A 4 X 4 superconducting Batcher-Banyan switch

A 4 X 4 superconducting Batcher-Banyan switch

3.5 GHz operation of a superconducting packet switch element

Clock-frequency and temperature margins of a high-temperature superconductor delay-line memory

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