Abstract-The Phase-II Upgrade of the ATLAS Muon Detector requires new electronics for the readout of the MDT drift tubes. The first processing stage, the Amplifier-Shaper-Discriminator (ASD), determines the performance of the readout for crucial parameters like time resolution, gain uniformity, efficiency and noise rejection. An 8-channel ASD chip, using the IBM 130 nm CMOS 8RF-DM technology, has been designed, produced and tested. The area of the chip is 2.2 x 2.9 mm 2 . We present results of detailed measurements as well as a comparision with simulation results of the chip behaviour at three different levels of detail.The HL-LHC at CERN will operate at peak luminosities factors of 5 7.5 beyond the original LHC design value of 10 34 cm −2 s −1 . The high luminosity is a challenge for the readout system of the Monitored Drift Tube chambers (MDT) in the ATLAS Muon Spectrometer [1] in two respects. Higher hit rates, mainly due to increased cavern background, drive data transmission to the rear end electronics to the limit of available bandwidth. In addition, the new operating parameters of the L1 trigger -latency up to 60 µs and trigger rates up to 400 kHz -call for a replacement of the entire readout chain of the MDT chambers.In this process of renewing the MDT readout, particular attention must be given to the first stage of the readout chain, the Amplifier with Shaping network and Discriminator (ASD) [2]. This stage determines critical quantities, like signal risetime, signal-to-noise performance and threshold uniformity among the 8 channels of the chip, which are decisive for system parameters like spatial resolution of the track coordinates (represented by the drift time in the MDT tubes) and tracking efficiency.To cope with these requirements, a chip was developed in the IBM 130 nm CMOS 8RF-DM technology. The design contains a preamplifier, three shaping stages and a discriminator (see Fig. 1). The chip can be operated in two output modes, the time-over-threshold (ToT) and the ADC mode. In the ADC mode, implemented as a Wilkinson ADC, the time elapsed between leading and trailing edge is proportional to the the charge inside a predefined integration window of about 15 ns, which is an approximate measure of the amplitude of the initial signal triggering the discriminator. The ADC information allows to apply a slewing correction to the time of threshold crossing (measurement of the drift time) and is