At-Speed Functional Built-In Self-Test Methodology for Processors

Abstract

Dependability of systems has become one of the most important engineering concerns. With new technologies new paradigms of testing are emerging. One of them is to make systems self-testing, and the quality of self-test is the key issue. In this paper, a new methodology of functional Built-In Self-Test is proposed, which stresses testing in dynamics to achieve the highest fault coverage. The main novelty of the proposed approach is in using the inherent functionality of systems for testing them at-speed in normal working conditions. The proposed self-test includes on-chip test application and response collection by using the native instructions of the processor under test. A hierarchical divide-and-conquer approach is applied. At component level, tests are targeting structural faults in components whereas at processor level, the functionality of the processor is used to apply structural tests to each component at-speed. Differently from similar approaches, the sequences of component test patterns are not needed to store in the chip under test, they will be generated on-line by the resources of the system. A framework for synthesis of self-test stimuli data is proposed.