Asynchronous Operation of Bufferless Crossbars

Passas, G.; Katevenis, Manolis

doi:10.1109/hpsr.2007.4281217

Cited by 5 publications

(2 citation statements)

References 15 publications

(24 reference statements)

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“…Note that each output operates asynchronously and independently of all other outputs, allowing fully distributed scheduling algorithms, in which the output scheduling complexity is O(N ). Finally, [13] discusses in details the asynchronous implementation of the classical iSLIP [14] scheduling algorithm. It highlights also that some traffic patterns may cause starvation problems.…”

Section: Input-queued Switch With Voqmentioning

confidence: 99%

Asynchronous vs synchronous input-queued switches

Bianco

Cuda

Giaccone

et al. 2014

Computer Communications

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POLITECNICO DI TORINO Repository ISTITUZIONALE Asynchronous vs synchronous input-queued switches / Bianco A.; Cuda D.; Giaccone P.; Neri F.. -STAMPA. -(2010). ((Intervento presentato al convegno IEEE GLOBECOM 2010 (Next Generation Networking Symposium) tenutosi a Miami, FL nel December 2010. Original Asynchronous vs synchronous input-queued switchesPublisher:Published Abstract-Input-queued (IQ) switches are one of the reference architectures for the design of high-speed packet switches. Classical results in this field refer to the scenario in which the whole switch transfers the packets in a synchronous fashion, in phase with a sequence of fixed-size timeslots, selected to transport a minimum-size packet. However, for switches with large number of ports and high bandwidth, maintaining an accurate global synchronization and transferring all the packets in a synchronous fashion is becoming more and more challenging. Furthermore, variable size packets (as in the traffic present in the Internet) require rather complex segmentation and reassembly processes and some switching capacity is lost due to partial filling of timeslots. Thus, we consider a switch able to natively transfer packets in an asynchronous fashion thanks to a simple and distributed packet scheduler. We investigate the performance of asynchronous IQ switches and show that, despite their simplicity, their performance are comparable or even better than those of synchronous switches. These partly unexpected results highlight the great potentiality of the asynchronous approach for the design of high-performance switches.

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Section: Input-queued Switch With Voqmentioning

confidence: 99%

Asynchronous vs synchronous input-queued switches

Bianco

Cuda

Giaccone

et al. 2014

Computer Communications

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“…However, synchronized packet-mode scheduling of non-buffered crossbar switches has some drawbacks. First, it may cause temporary flow starvation [16], [21]. When one input-output pair finishes transmitting the last cell of a packet, all the other pairs may still be in the middle of transmitting their packets and not available.…”

Section: Introductionmentioning

confidence: 99%

Packet-Mode Asynchronous Scheduling Algorithm for Partially Buffered Crossbar Switches

Karimi

Sun

Pan

et al. 2009

GLOBECOM 2009 - 2009 IEEE Global Telecommunications Conference

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Traditional crossbar switches use centralized scheduling algorithms with high time complexity. In contrast, buffered crossbar switches are capable of distributed scheduling due to crosspoint buffers, which decouple the dependency between inputs and outputs. However, crosspoint buffers are expensive on-chip memories. To reduce the hardware cost of buffered crossbar switches and make them scalable, we consider partially-buffered crossbar switches, whose crosspoint buffers can be of an arbitrarily small size and store only part of a packet instead of the entire packet. In this paper, we propose the Packet-mode Asynchronous Scheduling Algorithm (PASA) for partially buffered crossbar switches. PASA combines the features of both distributed and centralized scheduling algorithms. It works in an asynchronous mode and can directly handle variable length packets without Segmentation And Reassembly (SAR). We theoretically prove that, with a speedup of two, PASA achieves 100% throughput for any admissible traffic. We also show that outputs in PASA have a large probability to avoid the more timeconsuming centralized scheduling process, and thus make fast scheduling decisions. Finally, we present simulation data to verify the analytical results and evaluate the performance of PASA.

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Asynchronous vs Synchronous Input-Queued Switches

Bianco¹,

Cuda²,

Giaccone³

et al. 2010

2010 IEEE Global Telecommunications Conference GLOBECOM 2010

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Input-queued (IQ) switches are one of the reference architectures for the design of high-speed packet switches. Classical results in this field refer to the scenario in which the whole switch transfers the packets in a synchronous fashion, in phase with a sequence of fixed-size timeslots, selected to transport a minimum-size packet. However, for switches with large number of ports and high bandwidth, maintaining an accurate global synchronization and transferring all the packets in a synchronous fashion is becoming more and more challenging. Furthermore, variable size packets (as in the traffic present in the Internet) require rather complex segmentation and reassembly processes and some switching capacity is lost due to partial filling of timeslots. Thus, we consider a switch able to natively transfer packets in an asynchronous fashion thanks to a simple and distributed packet scheduler. We investigate the performance of asynchronous IQ switches and show that, despite their simplicity, their performance are comparable or even better than those of synchronous switches. These partly unexpected results highlight the great potentiality of the asynchronous approach for the design of high-performance switches.

show abstract

Asynchronous Operation of Bufferless Crossbars

Cited by 5 publications

References 15 publications

Asynchronous vs synchronous input-queued switches

Asynchronous vs synchronous input-queued switches

Packet-Mode Asynchronous Scheduling Algorithm for Partially Buffered Crossbar Switches

Asynchronous vs Synchronous Input-Queued Switches

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