Asynchronous MMC based Parallel SA Schemes for Multiobjective Standard Cell Placement

Sait, Sadiq M.; Zaidi, Ali Mustafa; Ali, Mustafa Imran

doi:10.1109/iscas.2006.1693658

Cited by 5 publications

(1 citation statement)

References 4 publications

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“…We have also implemented parallel SA [11], GA [8] and TS [6] for the same optimization problem and found that parallel cooperative searches best suited SA and GA, while a type I parallelization of TS gave the best speed-ups. Currently we are working on a fair and thorough comparison among these different parallelized metaheuristics.…”

Section: General Observationsmentioning

confidence: 99%

Evaluating parallel simulated evolution strategies for VLSI cell placement

Ali¹,

Zaidi²

2006

Proceedings 20th IEEE International Parallel &Amp; Distributed Processing Symposium

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Section: General Observationsmentioning

confidence: 99%

Evaluating parallel simulated evolution strategies for VLSI cell placement

Ali¹,

Zaidi²

2006

Proceedings 20th IEEE International Parallel &Amp; Distributed Processing Symposium

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Exploring Asynchronous MMC-Based Parallel SA Schemes for Multiobjective Cell Placement on a Cluster of Workstations

et al. 2011

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Simulated Annealing (SA) is a popular iterative heuristic used to solve a wide variety of combinatorial optimization problems. However, depending on the size of the problem, it may have large run-time requirements. One practical approach to speed up its execution is to parallelize it. In this paper, several parallel SA schemes based on the Asynchronous Multiple-Markov Chain model are explored. We investigate the speedup and solution quality characteristics of each scheme when implemented on an inexpensive cluster of workstations for solving a multi-objective cell placement problem. This problem requires the optimization of conflicting objectives (interconnect wire-length, power dissipation, and timing performance), and Fuzzy logic is used to integrate the costs of these objectives. Our goal is to develop several AMMC based parallel SA schemes and explore their suitability for different objectives: achieving near linear speedups while still meeting solution quality targets, and obtaining higher quality solutions in the least possible duration.

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