Asynchronous Arbiter Module

Pearce, R.C.; Field, James A.; Little, W.D.

doi:10.1109/t-c.1975.224339

Cited by 38 publications

(10 citation statements)

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“…If the arbiter avoids signaling simultaneous assent to distinct processors and the processors refrain from transmitting without receiving a grant, all will be well. The procedure corresponds exactly to that used by arbiters described, for example, in [14] and [18], and it captures the essence of such arbiters as in [19] and [20], whose task includes not only the exclusion of simultaneous access to shared resources, but the transfer of data as well. In order to avoid unnecessary complications we shall restrict our investigation to the single, crucial task of arbitrating between possibly competing requests.…”

Section: On Ideal Arbitersmentioning

confidence: 99%

Newtonian arbiters cannot be proven correct

Mendler

Stroup

1993

Form Method Syst Des

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Abstract. Computing hardware is designed by refining an abstract specification through various lower levels of abstraction to arrive at a transistor layout implemented in a physical medium. Formalizing the refinements-one task of the mathematical semantics of computation-involves proving that the device described at each level of abstraction does indeed behave as prescribed by the description at the next higher level. One obstacle to this goal that has long been recognized is that certain classes of behaviors can be physically realized only approximately. The notorious problem of metastable operation precludes, for example, the realization on classical principles of flipflops that react in bounded time to arbitrary input signals.The literature suggests that the difficulty lies ultimately in the specification's requiring that the realizing device react properly in bounded time. We show, however, that a simple-time-unbounded synchronization problem, namely, mutual exclusion by means of an arbiter, cannot be solved with perfect reliability using continuous, i.e., Newtonian, physical phenomena. In particular, for any physical device operating on Newtonian principles that satisfies specific assumptions concerning an arbiter's input-output behavior, there always exist competing requests to which it reacts by granting them all.

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Section: On Ideal Arbitersmentioning

confidence: 99%

Newtonian arbiters cannot be proven correct

Mendler

Stroup

1993

Form Method Syst Des

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“…If we include the necessary gates for realizing (2) and (3), the module design Mi is shown in Fig. 3.…”

Section: ) Its Request Was Recorded (Qi = 1)mentioning

confidence: 99%

“…In this asynchronous and modular design, two characteristics have been pursued: simplicity of design and the intent to reduce the problems related to possible metastable situations. several papers [2], [3]. It has been shown that the deductive method is faster than the parallel method for most circuits.…”

Section: Control Circuitmentioning

confidence: 99%

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Asynchronous Modular Arbiter

Calvo

Acha²

1986

IEEE Trans. Comput.

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“…Therefore, each PE needs two l-of-20 bus arbiters. A l-of-20 bus arbiter can be constructed from 19 1-to-2 arbiter modules [19 , each having 12 gates [20]. These gates can be constructe d from 54 transistors if CMOS technologyisused.…”

Section: Silicon Overhead Estimationmentioning

confidence: 99%

Performance modeling of the modified mesh-connected parallel computer

Wang

Nelson²,

Wu³

[1989] Proceedings. The 9th International Conference on Distributed Computing Systems

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A new message-passing computer architecture called the modified mesh-connected parallel computer (MMCPC) is proposed and studied. The MMCPC is desi ned to be a general-purpose parallel architecture suitable 8, wafer scale integration. Generalized stochastic Petri nets (GSPN) are used to model the behavior of the MMCPC. The GSPN performance modeling results show a need for a new processing element(PE). A new PE architecture, able to handle data processing and message passing concurrently, is proposed and the silicon overhead is estimated in comparison with transputer-like PE's. Based on the proposed PE, optimum sizes of the MMCPC for different program structures are derived. At last, a 2D FFT problem serves as an example to demonstrate that the MMCPC is indeed a cost-effective performance enhancement architecture to a real problem.

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Asynchronous Arbiter Module

Cited by 38 publications

References 1 publication

Newtonian arbiters cannot be proven correct

Newtonian arbiters cannot be proven correct

Asynchronous Modular Arbiter

Performance modeling of the modified mesh-connected parallel computer

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