Asynchronous adiabatic design of full adder using dual-rail domino logic

Kumar, Arvind; Somasundareswari, D.; Duraisamy, V.; Nair, Mithun. G.

doi:10.1109/iccic.2012.6510234

Cited by 3 publications

(4 citation statements)

References 22 publications

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“…The term is widely used in thermodynamic systems. In electronics it means charge conservation in each transfer [6]. In adiabatic systems the energy stored in the circuit can return to power supply in certain phases of the circuit operation.…”

Section: Adiabatic Logicmentioning

confidence: 99%

“…Using diodes causes irreversible charge transfer and reduces output voltage. In [2,6,7], complimentary pass transistor logic (CPAL) reduces power consumption using pass transistor. In [6] asynchronous adiabatic logic has been implemented using Dual Rail Domino Logic (DRDAAL).…”

Section: Introductionmentioning

confidence: 99%

“…In [2,6,7], complimentary pass transistor logic (CPAL) reduces power consumption using pass transistor. In [6] asynchronous adiabatic logic has been implemented using Dual Rail Domino Logic (DRDAAL). This method brings the advantage of asynchronous circuits to adiabatic logic.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Low Power Parallel Prefix Adder Design Using Two Phase Adiabatic Logic

Hassanzadeh

Shabani

2015

JEEE

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In this paper low power implementation of parallel prefix adders using two phase adiabatic logic has been investigated. A new structure has been proposed for the main blocks of parallel prefix adder. Three parallel prefix adders including Kogge-Stone, Brent-Kung and Ripple Carry have been considered. The effects of power clock frequency and loading capacitance on the new blocks have also been considered. Simulation results using 180nm technology parameters and trapezoidal waveform show an average of 34% power reduction in the main building blocks of the adder at 200MHz clock frequency. This power reduces to 54% for sine wave power clock waveform. This research suggests adiabatic implementation of parallel prefix adders for low power microprocessor and signal processing applications.

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Section: Adiabatic Logicmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Low Power Parallel Prefix Adder Design Using Two Phase Adiabatic Logic

Hassanzadeh

Shabani

2015

JEEE

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“…This full adder cell uses novel XOR, XNOR gates and transmission gates to generate the sum and carry out with 14 transistors half of the PMOS and another half NMOS. This full adder is designed using the pass transistors and transmission gates, Some of the research scholars designed full adder circuits with adiabatic circuit logic [11]- [13] to make energy efficient arithmetic circuits, which requires too many transistors. Due to this area and design complexity of circuit increases.…”

Section: Previous Workmentioning

confidence: 99%

A novel power-aware and high performance full adder cell for ultra-low power designs

Ramireddy¹,

Rovinara²

2014

2014 International Conference on Circuits, Power and Computing Technologies [ICCPCT-2014]

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The design of low power VLSI circuit is a challenging task at deep sub-micron technologies. Full adder is a basic key element of many arithmetic circuits like multiplexers, subtracters, dividers, etc.. . Since the technology is changing at a rapid pace, it is essential to develop and design new methodologies or circuits, which are going to reduce power consumption and worst case delay of circuits. In this regards, this paper is proposing a new circuit design for obtaining full adder functionality of 1-Bit. The proposed full adder is designed with 10-Transistors. The proposed 10-Transistor full adder uses two Low Power XOR gates and a two transistor multiplexer. All the designed circuits in this paper are captured and simulated using Virtuso Schematic Editor and Spectre simulator. These tools are part of Cadence Virtuoso Design Environment provided by Cadence Design Systems. Generic Process Design Kit(GPDK) 45nm technology file is used to get the transistor models. Prelayout simulation results turn out that the proposed 10-Transistor full adder performance better.

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