Asymptotically tight bounds for performing BMMC permutations on parallel disk systems

Cormen, Thomas H.; Wisniewski, Leonard F.

doi:10.1145/165231.165248

Cited by 19 publications

(12 citation statements)

References 12 publications

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“…Bilardi and Peserico [8] investigate further the complexity of designing algorithms without the knowledge architectural parameters. 2 Other attempts were directed towards extracting better performance by parallel memory hierarchies [32,33,14], where several blocks could be transferred simultaneously.…”

Section: Related Workmentioning

confidence: 99%

Towards a theory of cache-efficient algorithms

Sen

Chatterjee²,

Dumir

2002

J. ACM

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We describe a model that enables us to analyze the running time of an algorithm in a computer with a memory hierarchy with limited associativity, in terms of various cache parameters. Our model, an extension of Aggarwal and Vitter's I/O model, enables us to establish useful relationships between the cache complexity and the I/O complexity of computations. As a corollary, we obtain cache-optimal algorithms for some fundamental problems like sorting, FFT, and an important subclass of permutations in the single-level cache model. We also show that ignoring associativity concerns could lead to inferior performance, by analyzing the average-case cache behavior of mergesort. We further extend our model to multiple levels of cache with limited associativity and present optimal algorithms for matrix transpose and sorting. Our techniques may be used for systematic exploitation of the memory hierarchy starting from the algorithm design stage, and dealing with the hitherto unresolved problem of limited associativity.

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Section: Related Workmentioning

confidence: 99%

Towards a theory of cache-efficient algorithms

Sen

Chatterjee²,

Dumir

2002

J. ACM

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“…We have also shown that the algorithm of Cormen et al [8] for bit-matrixmultiply/complement (BMMC) permutation is sequence preserving and hence optimal in I-O time. Similarly, the inner loop of the algorithm for FFT and Permutation network in [3] is sequence-preserving and hence optimal.…”

Section: Matrix Transpose Algorithmmentioning

confidence: 75%

Algorithmic Ramifications of Prefetching in Memory Hierarchy

Verma

Sen

2006

High Performance Computing - HiPC 2006

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Abstract. External Memory models, most notable being the I-O Model [3], capture the effects of memory hierarchy and aid in algorithm design. More than a decade of architectural advancements have led to new features not captured in the I-O model -most notably the prefetching capability. We propose a relatively simple Prefetch model that incorporates data prefetching in the traditional I-O models and show how to design algorithms that can attain close to peak memory bandwidth. Unlike (the inverse of) memory latency, the memory bandwidth is much closer to the processing speed, thereby, intelligent use of prefetching can considerably mitigate the I-O bottleneck. For some fundamental problems, our algorithms attain running times approaching that of the idealized Random Access Machines under reasonable assumptions. Our work also explains the significantly superior performance of the I-O efficient algorithms in systems that support prefetching compared to ones that do not.

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“…Early work on I/O algorithms concentrated on algorithms for sorting and permutation related problems [1,15,23,24,34]. External sorting requires Θ(n log m n) I/Os, 1 which is the external-memory equivalent of the wellknown Θ(N log N) time bound for sorting in internal memory.…”

Section: Previous Results In I/o-efficient Computationmentioning

confidence: 99%

External-Memory Algorithms for Processing Line Segments in Geographic Information Systems

Arge¹,

Vengroff²,

Vitter³

1996

BRICS

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In the design of algorithms for large-scale applications it is essential to consider the problem of minimizing I/O communication. Geographical information systems (GIS) are good examples of such large-scale applications as they frequently handle huge amounts of spatial data. In this paper we develop efficient new external-memory algorithms for a number of important problems involving line segments in the plane, including trapezoid decomposition, batched planar point location, triangulation, red-blue line segment intersection reporting, and general line segment intersection reporting. In GIS systems, the first three problems are useful for rendering and modeling, and the latter two are frequently used for overlaying maps and extracting information from them. * An extended abstract version of this paper was presented at the Third Annual European Symposium on Algorithms (ESA '95).

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Asymptotically tight bounds for performing BMMC permutations on parallel disk systems

Cited by 19 publications

References 12 publications

Towards a theory of cache-efficient algorithms

Towards a theory of cache-efficient algorithms

Algorithmic Ramifications of Prefetching in Memory Hierarchy

External-Memory Algorithms for Processing Line Segments in Geographic Information Systems

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