Asymmetry Mitigation in IEEE 802.3 Ethernet for High-Accuracy Clock Synchronization

Exel, Reinhard; Bigler, Thomas; Sauter, Thilo

doi:10.1109/tim.2013.2280489

Cited by 23 publications

(16 citation statements)

References 11 publications

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“…Note that the γ s,k term corresponds to the frequent clock drift estimated by the syntonization mechanism, which is included for instance in PTP as we will cover in the subsequent sections. The variable deviation is frequently included in the skew [9], [10], thus giving:…”

Section: B Time Synchronization Conceptmentioning

confidence: 99%

A Survey of Clock Synchronization Over Packet-Switched Networks

Lévesque

Tipper

2016

IEEE Commun. Surv. Tutorials

112

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Abstract-Clock synchronization is a prerequisite for the realization of emerging applications in various domains such as industrial automation and the intelligent power grid. This paper surveys the standardized protocols and technologies for providing synchronization of devices connected by packet-switched networks. A review of synchronization impairments and the stateof-the-art mechanisms to improve the synchronization accuracy is then presented. Providing microsecond to sub-microsecond synchronization accuracy under the presence of asymmetric delays in a cost-effective manner is a challenging problem, and still an open issue in many application scenarios. Further, security is of significant importance for systems where timing is critical. The security threats and solutions to protect exchanged synchronization messages are also discussed.

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Section: B Time Synchronization Conceptmentioning

confidence: 99%

A Survey of Clock Synchronization Over Packet-Switched Networks

Lévesque

Tipper

2016

IEEE Commun. Surv. Tutorials

112

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“…1b, the signal flow graph is one-way. However, a networked system is always composed of full duplex links, and the link delays are asymmetric (Exel et al, 2014). Thus, in fact, we need two signal flow graphs to model the end-to-end delays of a networked system.…”

Section: System Modelingmentioning

confidence: 99%

End-to-end delay analysis for networked systems

Shen

et al. 2015

Frontiers Inf Technol Electronic Eng

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End-to-end delay measurement has been an essential element in the deployment of real-time services in networked systems. Traditional methods of delay measurement based on time domain analysis, however, are not efficient as the network scale and the complexity increase. We propose a novel theoretical framework to analyze the end-to-end delay distributions of networked systems from the frequency domain. We use a signal flow graph to model the delay distribution of a networked system and prove that the end-to-end delay distribution is indeed the inverse Laplace transform of the transfer function of the signal flow graph. Two efficient methods, Cramer's rule-based method and the Mason gain rule-based method, are adopted to obtain the transfer function. By analyzing the time responses of the transfer function, we obtain the end-to-end delay distribution. Based on our framework, we propose an efficient method using the dominant poles of the transfer function to work out the bottleneck links of the network. Moreover, we use the framework to study the network protocol performance. Theoretical analysis and extensive evaluations show the effectiveness of the proposed approach.

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“…In [1], we presented a method for measuring and mitigating the link asymmetry by swapping the receive and transmit line of a 100Base-TX Ethernet link at the network connection start-up. Although this approach can remove the majority of the asymmetry-induced clock offset, it has the drawback of increasing the start-up time of the network link by multiple seconds to minutes depending on the clock stability and line-swapping delay.…”

Section: B Asymmetry Mitigation In Ethernetmentioning

confidence: 99%

“…According to this standard, Ethernet cables may have a delay difference of up to 50 ns per line pair resulting in ±25 ns asymmetry per link. The asymmetry of real cables is often much lower, such as about ±2 ns for a 60 m cable as measured in [1]. Still, the asymmetryinduced synchronization offset can be considered as one of the main reasons why PTP with hardware timestamping can hardly reach accuracies below one nanosecond over copperbased Ethernet.…”

Section: Introductionmentioning

confidence: 99%

Out-of-band asymmetry removal for high accuracy clock synchronization in 100Base-TX

Bigler

Exel

2013

2013 IEEE International Symposium on Precision Clock Synchronization for Measurement, Control and Communication (ISPCS) Proceed

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The IEEE 1588 standard enables accurate clock synchronization in a distributed network by synchronizing multiple slave clocks to one master. To reduce the synchronization offset, IEEE 1588 compensates for the propagation delay between master and slave by round-trip measurements and the assumption of known link asymmetries. Yet, the determination of the asymmetries is out of scope of the standard. Therefore, state-ofthe-art implementations often neglect the presence of asymmetry which leads to a clock offset between master and slaves.In this paper we propose an asymmetry determination method for 100Base-TX using out-of-band Chirp Spread Spectrum signaling. In contrast to the round-trip measurements by IEEE 1588 event messages, the proposed solution is able to measure each individual link delay and is therefore capable of resolving the asymmetry. The practical feasibility of the proposed solution is shown by an FPGA-based prototype solution, which reveals that our approach enables sub-nanosecond synchronization even over (asymmetric) CAT5 cabling.

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Asymmetry Mitigation in IEEE 802.3 Ethernet for High-Accuracy Clock Synchronization

Cited by 23 publications

References 11 publications

A Survey of Clock Synchronization Over Packet-Switched Networks

A Survey of Clock Synchronization Over Packet-Switched Networks

End-to-end delay analysis for networked systems

Out-of-band asymmetry removal for high accuracy clock synchronization in 100Base-TX

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