Asymmetry and mismatch in CMOSFETs with source/drain regions fabricated by various ion-implantation methods

Ohzone, T.; Miyakawa, T.; Yabu, T.; Odanaka, S.

doi:10.1109/icmts.1996.535640

Cited by 4 publications

(3 citation statements)

References 10 publications

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“…Consequently the most reasonable choice may be case (D) because of the moderate ( I~+ I D~) / I D D /~/ T P~ values and reasonably lower Imn as well as asymmetry/mismatch [4] and punchthrough immunity of CMOSFET (71. The inferior case was (A) because of lower (I&'tIDp)/IDD/f and highest I B~/ I~* The worst case may be case (A) with offset between source and gate, because ID, was about 10 % lower than the former (A) case and f was the lowest.…”

Section: Resultsmentioning

confidence: 99%

“…The 7" tilt-angle four-times rotating implantation method [5] and the oblique-rotating implantation technique [6] were proposed to improve the symmetric impurity profiles. 0"-implantation is also useful because the shadowing effect is eliminated and the comprehensive comparison between electrical characteristics of CMOSFETs fabricated by 7"-and 0"-implantation [7] and A&M characteristics of CMOSFETs fabricated by four ion-implantation methods [4] have been reported so far. However the influence of the asymmetric source/drain fabricated by various ionimplantation methods on the circuit performance has not been reported, except the reliability of CMOS ringoscillator fabricated by the oblique-rotating implantation technique [SI. In this paper, the circuit performance was evaluated using 0.5 pm CMOS ring-oscillators fabricated by four kinds of asymmetric/symmetric ion-implantation methods.…”

Section: Introductionmentioning

confidence: 98%

“…However the shadowing effect by the gate electrode is occurred due to the tilt-angle implantation resulting in asymmetric impurity profiles of the source/drain regions. The source/drain asymmetry introduces degradation of current drivability and reliability of LDD-type MOSFETs [3] as well as serious asymmetry and mismatch (hereafter called A&M) in CMOSFETs [4]. The 7" tilt-angle four-times rotating implantation method [5] and the oblique-rotating implantation technique [6] were proposed to improve the symmetric impurity profiles.…”

Section: Introductionmentioning

confidence: 99%

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Performance evaluation of CMOS ring-oscillators with source/drain regions fabricated by asymmetric/symmetric ion-implantation

Ohzone

Miyakawa²,

Matsuda³

et al.

1997 IEEE International Conference on Microelectronic Test Structures Proceedings

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well. Those parameters were discussed in comparison with saturation drain current and substrate current of CMOSFET. 0.5 pm CMOS ring-oscillators with LDD-type surfacechannel n-MOSFETs and EPS-type buried-channel pMOSFETs with asymmetridsymmetric source/drain fabricated by four kinds of ion-implantation methods 2. EXPERIMENTS were measured for evaluating the circuit performance. Figure 1 shows perspective views of a CMOSET with The ion-implantation methods were correlated to supply-(a) an LDD-type surface-channel n-MOSFET and (b) a current/oscillation-frequencyldelay-power product and buried-channel p-MOSET (hereafter called EPS-type p substrate current of the ring-Oscilk+tor. The most MOSFET) with n --F k e t s used as efficient punchthrough preferable implantation method was the symmetric 7"X4-stops (EPS). The MOSFETs were fabricated by an n-well implantation in terms Of circuit performance, CMOS process with the trench isolation [9]. The n-w& asymetq/mismatch and punchthrough with a depth of 3.0 p,m and a peak concentration of CMOSFET.1.5~1016 cm-3 was formed in p-type silicon substrate of lxlOl5 cm-3. Shallow vertical trenches of 0.5 pm depth were formed in the substrate. For n-MOSFETs, boron ions were implanted into the trench sidewalls as a channel Of

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Section: Resultsmentioning

confidence: 99%