Asymmetric source/drain offset structure for reduced leakage current in polycrystalline‐silicon thin‐film transistors

Abstract

Abstract— An asymmetric source/drain offset structured (AOS) polycrystalline‐silicon (poly‐Si) thin‐film transistor (TFT) has ben developed by employing alternating magnetic‐field‐enhanced rapid thermal annealing (AMFERTA). The realized AOS poly‐Si TFT, with long drain‐side offset length LOff1 and short source‐side offset length LOff2, considerably suppresses leakage current without sacrificing ON‐current. The offset regions of the AOS TFT are naturally lightly doped due to the diffusion of n+ ions by AMFERTA crystallization. The fabrication process of the AOS TFT does not require any additional offset mask step or doping process. Experimental results show that the leakage current is considerably suppressed when the drain‐side offset length LOff1 is larger than 1.25 μm.