Assessment of flip chip assembly and reliability via reflowable underfill

Wang, Tie; Chew, T.H.; Lum, Christopher W.; Chew, Yixin; Miao, Ping; Foo, Lo Keng

doi:10.1109/ectc.2001.927875

Cited by 10 publications

(3 citation statements)

References 2 publications

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“…This energy change in Gibbs free energy for the application of FCIP happening on the smooth surface of hot molten solder is illustrated in figure 1, in which we assume the heterogeneous nucleation being a reversible, isothermal thermodynamic process. Thus, the heterogeneous nucleation accounts for void nucleation on the smooth solder surface, given by equation (1) [15,19,20,26,[30][31][32],…”

Section: Heterogeneous Void Nucleation Modelmentioning

confidence: 99%

“…The flip chip in package (FCIP) technology has been widely used for high performance electrical devices such as microprocessors, graphic devices and high speed memory applications. The high performance FCIP demands an advanced material formulation, no-flow underfill, to achieve high, stable yields due to the complexity of high I/O (3500 ) counts and the fine-pitch ( 100 µm) structure [1][2][3][4]. Indeed, a high, reliable yield assembly process has been developed and reported in [5][6][7] with high I/O (3500 ) counts and fine-pitch ( 100 µm) flip chip using a no-flow underfill.…”

Section: Introductionmentioning

confidence: 99%

“…However, a large number of voids have been observed on the surface of solder bumps on the chip. The underfill voiding is the critical defect affecting the thermal reliability performance of FCIP [1,2,5,6].…”

Section: Introductionmentioning

confidence: 99%

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A numerical study of void nucleation and growth in a flip chip assembly process

Zhou

Baldwin

2010

Modelling Simul. Mater. Sci. Eng.

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In this study, we develop mathematical models and numerical simulations of void nucleation and growth induced by the chemical reaction in the flip chip package assembly process using a no-flow underfill. During the thermal assembly process, the underfill chemically reacts to the oxidation of solders I/O on the chip, achieving interconnection between chip and substrate. The chemical reaction causes a large number of voids in the thermal reflow process. The voids have been considered as a critical defect, reducing the life of the thermal reliability. This study investigates the mechanism of void nucleation and growth based on classical bubble nucleation theory and bubble dynamics, respectively. This knowledge can provide a theoretical foundation to achieve a void-free assembly process and high reliability performance.

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Section: Heterogeneous Void Nucleation Modelmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A numerical study of void nucleation and growth in a flip chip assembly process

Zhou

Baldwin

2010

Modelling Simul. Mater. Sci. Eng.

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Near void free hybrid no-flow underfill flip chip process technology

Colella

Baldwin

2004 Proceedings. 54th Electronic Components and Technology Conference (IEEE Cat. No.04CH37546)

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Development of three-dimensional multichip module based on embedded substrate with multiple interconnections

Geng

et al. 2008

2008 International Conference on Electronic Packaging Technology &Amp; High Density Packaging

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A new type of 3D multichip module (3D-MCM) for wireless sensor network was developed based on a kind of embedded FR-4 substrate for the wireless sensor network, in which FCOB (flip-chip on board), COB(chip on board), BGA(ball grid array) technologies, wirebonding and flip-chip interconnection technologies were combined together. The PBGA device and bare die were hybrid-integrated on the embedded multi-layer FR-4 substrate. By solder ball placement and reflow the BGA was formed at the bottom of 3D-MCM, and solder balls with different melting points were used for initial and final vertical interconnections for the sake of compatibility of all levels interconnections of BGA by reflow soldering. The application of embedded substrate solved the problem that the top surface of the encapsulated chip overtops the solder balls in the condition that the chip was assembled in the same side of substrate with BGA. The thermal management was conducted and the thermal related reliability of 3D-MCM were simulated and evaluated respectively. This kind of packaging structure satisfies the electrical performance and thermal requirement, and meets the challenge of minimization, high reliability and low cost of the package design for the wireless network.

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Assessment of flip chip assembly and reliability via reflowable underfill

Cited by 10 publications

References 2 publications

A numerical study of void nucleation and growth in a flip chip assembly process

A numerical study of void nucleation and growth in a flip chip assembly process

Near void free hybrid no-flow underfill flip chip process technology

Development of three-dimensional multichip module based on embedded substrate with multiple interconnections

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