Assessing the area/power/performance tradeoffs for an integrated fully-digital, large-scale 3D-ultrasound beamformer

Abstract

High-frame-rate and high-resolution 3D medical ultrasound imaging imposes high requirements on the involved processing hardware. Several thousands of analog signals need to be processed in many steps to obtain a final image. Fully digital beamforming makes it possible to achieve high image quality coupled with extreme flexibility. Unfortunately, digital beamforming imposes staggering requirements on main memory bandwidth caused by the loading of off-chip stored beamforming delays. In this paper we present the first fully-digital integrated beamformer that is able to compute 269.3 M focal points (FP) per second from 10 000 receive channels, and which does not require off-chip main memory. This is enabled by our novel delay approximation circuit that exploits temporal correlation between subsequent computations and thereby allows to compute the delays for beamforming online. To estimate the area and power requirements, the complete system was designed and the beamformer core was evaluated for a 130 nm CMOS technology. The estimated complexity per channel is 37.2 kGE and the corresponding power dissipation was estimated with 48 mW.

Tackling the Bottleneck of Delay Tables in 3D Ultrasound Imaging

“…We first revisit our previous works [9], [7] with increased emphasis on the delay approximation logic and some accuracy improvements. We also describe an alternative approach, based on storing a small reference delay table that serves as the basis for runtime delay calculation; this design stands out for its moderate FPGA resource occupation.…”

“…In [9], [7], we have presented an architecture to compute the two-way propagation delay efficiently and accurately. We refer the reader to those papers for more details and present just a brief summary here (see Figure 2).…”

“…To fulfill the throughput demands of 3D ultrasound imaging, it was shown in [7] that this unit must be instantiated once per transducer element (10000 times) with an achievable frame rate of about 1 fps per 20 MHz of operating frequency. …”

“…As a guideline, we chose in [9], [7] to bound the maximum absolute error of the square root approximation such that the error of the delay selection error is ±1 sample. Setting δ = 0.25, the approximation error can be assumed to be equally distributed in the interval (− 1 4 , 1 4 ).…”

“…First, we will revisit an architecture originally presented in [7], where all delays are computed on-the-fly with an optimized circuit. This architecture was originally developed with an ASIC target in mind, and in this paper we will assess its implementation on an FPGA target.…”