Aspect driven compilation for dataflow designs

dfesnippets: An Open-Source Library for Dataflow Acceleration on FPGAs

“…To illustrate the productivity gains achievable by the applications components we note that recent software frameworks such as experimental compilers [12] and resource management frameworks [13] for FPGA based systems can utilise these applications directly as benchmarks. Prototypes for these projects require 4123 and 3880 lines of code respectively, while the benchmarks require 2050 and 2924 lines of code respectively.…”

“…An application component which provides a collection of full applications to be used as case-studies for the development of frameworks and tools for FPGA based programming. These applications have been used in several research projects and publications [12][13][14][15][16]. Although we will not cover this in greater detail due to lack of space, the library also contains: 1) header only C++ libraries implementing useful functionality for managing and benchmarking DFE projects ranging from timing utilities to APIs for reordering sparse matrix data in preparation for FPGA execution; 2) tools for creating and managing projects such as to compile, generate and manage multiprocess and multi-node hardware compilation, and automatically extract and tabulate resource usage and generate reports; 3) comprehensive, automated test suite, testing each design to ensure it is functionally correct and it meets timing and resource usage constraints.…”

Towards Automatic High-Level Code Deployment on Reconfigurable Platforms: A Survey of High-Level Synthesis Tools and Toolchains

“…FAST (Facile Aspect-driven Source Transformation) [138] is a C-based DSL to describe compute-intensive parts of an application as high-level dataflow representations. FAST functions (the "high-level DFG representation" in path 3b ) can be embedded within a C application, and are invoked via specific annotations to indicate alternate hardware implementation.…”

“…LARA allows non-functional concerns such as optimisation and transformation strategies to be developed and maintained independently from the original application source code. These are described using LARA apects, which FIGURE 20: FAST-LARA design flow [138] can developed independently from the application and reused for different applications, thus improving productivity. There are four types of aspects: system aspects capture transformations and optimisation strategies that affect the whole application, such as hardware/software partitioning and runtime reconfiguration; architectural aspects focus on lowlevel design optimisations to improve timing, resource usage or exploit specialised architectural features; exploration aspects deal with strategies to generate multiple designs to find an optimal implementation based on user-specified constraints; and development aspects that relate to concerns that have an impact on the design process, such as debugging, kernel simulation and improving compilation speed.…”

High performance in the cloud with FPGA groups

“…These descriptions can also be automatically derived from higher-level programming languages similar to C, Java or OpenCL [9], [11]. However, to obtain the best possible performance, FPGA programmers must still have a deep understanding of the mapping between a high-level program and its low-level translation, and annotate their code with appropriate optimization guidelines [12]. Efficient programming of FPGAs therefore requires specific training and experience, which effectively creates a barrier to entry for new developers to exploit the full potential of FPGAs.…”