AsmDB: Understanding and Mitigating Front-End Stalls in Warehouse-Scale Computers

Nagendra, Nayana Prasad; Ayers, Grant; August, David I.; Cho, Hyoun Kyu; Kanev, Svilen; Kozyrakis, Christos; Krishnamurthy, Trivikram; Litz, Heiner; Moseley, Tipp; Ranganathan, Parthasarathy

doi:10.1109/mm.2020.2986212

Cited by 9 publications

(19 citation statements)

References 4 publications

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“…Specifically, on a suite of contemporary industrial server workloads, we find that over 40% of all STLB misses are caused by instruction references. Our findings corroborate the conclusions of previous industry works showing iSTLB pressure to be a performance bottleneck in their workloads [54,62,65].…”

Section: Introductionsupporting

confidence: 91%

“…Figure 3 presents the average MPKI rates of the L1 I-cache, the I-TLB, and the STLB (considering only the instruction misses) for the SPEC and the QMM workloads. We observe that (i) the QMM workloads experience an order of magnitude more instruction misses in the three hardware structures compared to the SPEC workloads, corroborating the conclusions of prior industrial works from Google [54,62], presented in Section 3.1, and (ii) the iSTLB MPKI rates of the QMM workloads are similar to the ones of the Java DaCapo and Java Renaissance workloads (Section 3.1).…”

Section: Analyzing Industrial Server Workloadssupporting

confidence: 84%

“…We also analyze the SPEC CPU 2006 [2] and SPEC CPU 2017 [10] benchmark suites, but we find that these workloads have an iSTLB MPKI of 0.5 or less, so they are not considered in our evaluation. However, we use the SPEC CPU workloads in Section 3 to show that we are consistent with the conclusions of previous works [54,62].…”

Section: Methodssupporting

confidence: 76%

“…Modern server workloads have massive instruction working sets that span many levels of the software stack, making the front-end of the processor a major performance pain point [47]. Indeed, recent work from Google [54,62] demonstrates that their server workloads face severe problems due to pressure on front-end structures.…”

Section: Front-end Bottleneckmentioning

confidence: 99%

“…Recent work [54,62,65,83] has shown that modern server and datacenter applications not only have big datasets, but also large code footprints. Huge binaries and deep software stacks cause frequent instruction cache and instruction TLB misses, compromising performance due to unavoidable pipeline stalls.…”

Section: Introductionmentioning

confidence: 99%

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Morrigan: A Composite Instruction TLB Prefetcher

Vavouliotis¹,

Alvarez

Grot

et al. 2021

MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture

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The effort to reduce address translation overheads has typically targeted data accesses since they constitute the overwhelming portion of the second-level TLB (STLB) misses in desktop and HPC applications. The address translation cost of instruction accesses has been relatively neglected due to historically small instruction footprints. However, state-of-the-art datacenter and server applications feature massive instruction footprints owing to deep software stacks, resulting in high STLB miss rates for instruction accesses.This paper demonstrates that instruction address translation is a performance bottleneck in server workloads. In response, we propose Morrigan, a microarchitectural instruction STLB prefetcher whose design is based on new insights regarding instruction STLB misses. At the core of Morrigan there is an ensemble of table-based Markov prefetchers that build and store variable length Markov chains out of the instruction STLB miss stream. Morrigan further employs a sequential prefetcher and a scheme that exploits page table locality to maximize miss coverage. An important contribution of the work is showing that access frequency is more important than access recency when choosing replacement candidates. Based on this insight, Morrigan introduces a new replacement policy that identifies victims in the Markov prefetchers using a frequency stack while adapting to phase-change behavior. On a set of 45 industrial server workloads, Morrigan eliminates 69% of the memory references in demand page walks triggered by instruction STLB misses and improves geometric mean performance by 7.6%. CCS CONCEPTS• Software and its engineering → Virtual memory; • Applied computing → Data centers.

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Section: Introductionsupporting

confidence: 91%

Section: Analyzing Industrial Server Workloadssupporting

confidence: 84%

Section: Methodssupporting

confidence: 76%

Section: Front-end Bottleneckmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Morrigan: A Composite Instruction TLB Prefetcher

Vavouliotis¹,

Alvarez

Grot

et al. 2021

MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture

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A Storage-Effective BTB Organization for Servers

Asheim

Grot

Kumar

2023

2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA)

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Many contemporary applications feature multimegabyte instruction footprints that overwhelm the capacity of branch target buffers (BTB) and instruction caches (L1-I), causing frequent front-end stalls that inevitably hurt performance. BTB capacity is crucial for performance as a sufficiently large BTB enables the front-end to accurately resolve the upcoming execution path and steer instruction fetch appropriately. Moreover, it also enables highly effective fetch-directed instruction prefetching that can eliminate a large portion L1-I misses. For these reasons, commercial processors allocate vast amounts of storage capacity to BTBs.This work aims to reduce BTB storage requirements by optimizing the organization of BTB entries. Our key insight is that storing branch target offsets, instead of full or compressed targets, can drastically reduce BTB storage cost as the vast majority of dynamic branches have short offsets requiring just a handful of bits to encode. Based on this insight, we size the ways of a set associative BTB to hold different number of target offset bits such that each way stores offsets within a particular range. Doing so enables a dramatic reduction in storage for target addresses. Our final design, called BTB-X, uses an 8-way set associative BTB with differently sized ways that enables it to track about 2.24x more branches than a conventional BTB and 1.3x more branches than a storage-optimized state-of-the-art BTB organization, called PDede, with the same storage budget.

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Research on Mobile Data Model System for Optimizing the Performance of Computer Web Front End

Meiyan¹

2021

2021 IEEE International Conference on Data Science and Computer Application (ICDSCA)

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AsmDB: Understanding and Mitigating Front-End Stalls in Warehouse-Scale Computers

Cited by 9 publications

References 4 publications

Morrigan: A Composite Instruction TLB Prefetcher

Morrigan: A Composite Instruction TLB Prefetcher

A Storage-Effective BTB Organization for Servers

Research on Mobile Data Model System for Optimizing the Performance of Computer Web Front End

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