ASIIST: Application Specific I/O Integration Support Tool for Real-Time Bus Architecture Designs

Nam, Min-Young; Pellizzoni, Rodolfo; Sha, Lui; Bradford, Richard

doi:10.1109/iceccs.2009.31

Cited by 20 publications

(7 citation statements)

References 12 publications

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“…The I/O bus is another example. When a new task is invoked, the I/O bus can carry the information of a previous task [16]. In this case, timing delay can be used to complete the previous task.…”

Section: Security and Schedulingmentioning

confidence: 99%

Preemptive Real-Time Scheduling Incorporating Security Constraint for Cyber Physical Systems

Baek

Lee

et al. 2016

IEICE Trans. Inf. & Syst.

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SUMMARYSince many cyber-physical systems (CPSs) manipulate security-sensitive data, enhancing the quality of security in a CPS is a critical and challenging issue in CPS design. Although there has been a large body of research on securing general purpose PCs, directly applying such techniques to a CPS can compromise the real-time property of CPSs since the timely execution of tasks in a CPS typically relies on real-time scheduling. Recognizing this property, previous works have proposed approaches to add a security constraint to the real-time properties to cope with the information leakage problem that can arise between real-time tasks with different security levels. However, conventional works have mainly focused on non-preemptive scheduling and have suggested a very naive approach for preemptive scheduling, which shows limited analytical capability. In this paper, we present a new preemptive fixed-priority scheduling algorithm incorporating a security constraint, called lowest security-level first (LSF) and its strong schedulability analysis to reduce the potential of information leakage. Our simulation results show that LSF schedulability analysis outperforms state-of-the-art FP analysis when the security constraint has reasonable timing penalties.

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Section: Security and Schedulingmentioning

confidence: 99%

Preemptive Real-Time Scheduling Incorporating Security Constraint for Cyber Physical Systems

Baek

Lee

et al. 2016

IEICE Trans. Inf. & Syst.

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“…Modeling complex COTS interconnections and estimating delay and buffer requirements for peripheral flows can be done in an AADL-based environment [11]. An eventbased model may be used to estimate delay for both computation and communication activities in a multicore systemon-chip [18].…”

Section: Related Workmentioning

confidence: 99%

“…Due to the lack of real-time prioritization, data I/O transactions travelling through the COTS bus into or out of main memory can suffer unpredictable delay and cause deadline misses [11]. Unfortunately, end-to-end real-time guarantees can not be achieved unless both tasks and I/O data transactions are properly processed in a prioritized manner.…”

Section: Introductionmentioning

confidence: 99%

Real-Time Control of I/O COTS Peripherals for Embedded Systems

Bak

Betti

Pellizzoni

et al. 2009

2009 30th IEEE Real-Time Systems Symposium

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Real-time embedded systems are increasingly being built using commercial-off-the-shelf (COTS) components such as mass-produced peripherals and buses to reduce costs, timeto-market, and increase performance. Unfortunately, COTS interconnect systems do not usually guarantee timeliness, and might experience severe timing degradation in the presence of high-bandwidth I/O peripherals. To address this problem, we designed a real-time I/O management system comprised of 1) real-time bridges, and 2) a reservation controller. The proposed framework is used to transparently put the I/O subsystem of a COTS-based embedded system under the discipline of real-time scheduling. We also discuss computing a delay bound for I/O data transactions and determining worst-case buffer size. Finally, we demonstrate experimentally that our prototype real-time I/O management system successfully prioritizes I/O traffic and guarantees its timeliness.

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“…Before reaching main memory, peripheral requests are typically buffered in the interconnection. Therefore, all peripheral requests coming from the same interconnection are aggregated (see [4] for details) into a single buffered flow α * i (t): for any interval of length t, α * i (t) is the maximum amount of time required by the aggregated peripheral to perform DMA operations in main memory. Each core P E i is characterized by a parameter C i , which is the time interval (assumed to be fixed) needed to service a memory request.…”

Section: Introductionmentioning

confidence: 99%

Worst case delay analysis for memory interference in multicore systems

Pellizzoni

Schranzhofery

Cheny

et al. 2010

2010 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE 2010)

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133

115

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Abstract-Employing COTS components in real-time embedded systems leads to timing challenges. When multiple CPU cores and DMA peripherals run simultaneously, contention for access to main memory can greatly increase a task's WCET. In this paper, we introduce an analysis methodology that computes upper bounds to task delay due to memory contention. First, an arrival curve is derived for each core representing the maximum memory traffic produced by all tasks executed on it. Arrival curves are then combined with a representation of the cache behavior for the task under analysis to generate a delay bound. Based on the computed delay, we show how tasks can be feasibly scheduled according to assigned time slots on each core.

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ASIIST: Application Specific I/O Integration Support Tool for Real-Time Bus Architecture Designs

Cited by 20 publications

References 12 publications

Preemptive Real-Time Scheduling Incorporating Security Constraint for Cyber Physical Systems

Preemptive Real-Time Scheduling Incorporating Security Constraint for Cyber Physical Systems

Real-Time Control of I/O COTS Peripherals for Embedded Systems

Worst case delay analysis for memory interference in multicore systems

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