ASIC Implementation of Area-Efficient, High-Throughput 2-D IIR Filter Using Distributed Arithmetic

Kumar, Prashant; Shrivastava, Prabhat Chandra; Tiwari, Manish; Dhawan, Amit

doi:10.1007/s00034-017-0698-z

Cited by 21 publications

(9 citation statements)

References 16 publications

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“…The ADP and PDP of the proposed diagonal symmetry filter architecture are decreased by 94% and 88% when compared to the filter architecture of Mohanty et al [3] M o h a n t y e t a l . [ 3 ] K u m a r [ 7 ] K u m a r e t a l . [ 8 ] A l a w a d e t a l .…”

Section: Implementation and Resultsmentioning

confidence: 99%

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Implementation of block-based diagonal and quadrantal symmetry type 2D-FIR filter architectures using DA technique

Reddy,

Juliet,

Thuraka

et al. 2024

Computers and Electrical Engineering

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Section: Implementation and Resultsmentioning

confidence: 99%

“…Further optimization is achieved by Common Subexpression Elimination (CSE) techniques. Kumar et al [7,8] implemented the 2D FIR and IIR filter architectures using DA methodologies. In these works, the block processing and DA concepts are combined to attain efficient hardware structures for filters.…”

Section: Literature Surveymentioning

confidence: 99%

Implementation of block-based diagonal and quadrantal symmetry type 2D-FIR filter architectures using DA technique

Reddy,

Juliet,

Thuraka

et al. 2024

Computers and Electrical Engineering

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“…Lowering connection length may further improve route propagation by reducing the total activity of signal transitions associated with each filter tap. Reconfigurable mode was suggested in [20] using a hardware-based look-up table (HLUT). The number of adders and memory elements utilised in the FIR structure may be reduced significantly due to hardware sharing across the many internal blocks.…”

Section: Related Workmentioning

confidence: 99%

An efficient high performance reconfigurable canonical sign digit architecture for software defined radio

Chalampalem,

Pidugu

2024

IJRES

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Software defined radios (SDRs) are highly motivated for wireless device modelling due to their flexibility and scalability over alternative wireless design options. The evolutionary structure of finite impulse response (FIR) filters was designed for a proposed reconfigurable canonical sign digit (CSD) approach. Considering the complex trade-off, this is accomplished with many FIR taps, which is a challenging assignment. On the baseband processing side, design is given with parameterization-controlled FIR filter tap selection. Optimal processing models to overcome the reconfigurable design issues associated with the SDR system for a multi-standard wireless communication system root cosine filter standard are often used to implement multiple FIR channelization topologies, each of which is tied to a particular in-phase and quadrature (IQ) symbol. Additionally, it demonstrates the viability of using a multi-modulation baseband modulator in the SDR system for next-generation wireless communication systems to maximise adaptability with the least amount of computational complexity overhead. The proposed multiplier-less FIR filter-based reconfigurable baseband modulator, according to the experimental results, offers a 6% complexity reduction and a 47% improvement in performance efficiency over the current SDR system.

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“…It is necessary to use rewritable RAM based LUT instead of ROM based LUT for reconfigurable DA based FIR filter whose filter coefficients alter dynamically. Another method is to store the analog domain coefficients using serial digital to analog converters, resulting in mixed-signal architectures [6].…”

Section: Related Workmentioning

confidence: 99%

Design and implementation of DA FIR filter for bio-inspired computing architecture

Prashanth

Ahmed

Kounte

2021

IJECE

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This paper elucidates the system construct of DA-FIR filter optimized for design of distributed arithmetic (DA) finite impulse response (FIR) filter and is based on architecture with tightly coupled co-processor based data processing units. With a series of look-up-table (LUT) accesses in order to emulate multiply and accumulate operations the constructed DA based FIR filter is implemented on FPGA. The very high speed integrated circuit hardware description language (VHDL) is used implement the proposed filter and the design is verified using simulation. This paper discusses two optimization algorithms and resulting optimizations are incorporated into LUT layer and architecture extractions. The proposed method offers an optimized design in the form of offers average miminimizations of the number of LUT, reduction in populated slices and gate minimization for DA-finite impulse response filter. This research paves a direction towards development of bio inspired computing architectures developed without logically intensive operations, obtaining the desired specifications with respect to performance, timing, and reliability.

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ASIC Implementation of Area-Efficient, High-Throughput 2-D IIR Filter Using Distributed Arithmetic

Cited by 21 publications

References 16 publications

Implementation of block-based diagonal and quadrantal symmetry type 2D-FIR filter architectures using DA technique

Implementation of block-based diagonal and quadrantal symmetry type 2D-FIR filter architectures using DA technique

An efficient high performance reconfigurable canonical sign digit architecture for software defined radio

Design and implementation of DA FIR filter for bio-inspired computing architecture

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