ASIC implementation of a modified QR decomposition for tree search based MIMO detection

Abstract

Multiple-antenna systems offer very attractive gains in data rates and transmission reliability. Therefore, they are employed in many modern communication standards. However, the detection and separation of these multiple data streams can be very complex. For tree search based detection methods, a channel preprocessing is mandatory which consists mainly of a QR matrix decomposition.We propose a modification of the standard QR matrix decomposition which simplifies the tree search while not increasing the complexity of the QR decomposition. We present hardware architectures of the original and the modified QR decomposition. The resulting ASIC implementation in 65nm technology runs at a maximum clock frequency of 370 MHz and consumes an area of 0.14mm 2 . The power consumption at the specified clock frequency of 300 MHz is only 6.8mW .

Design of fine-grained sequential approximate circuits using probability-aware fault emulation

“…TABLE I. THE BENCHMARK CIRCUITS USED FOR THIS EVALUATION Name Description Flip-flops Technology fpu100 [17] 32-bit floating point unit 2030 Synopsys 90nm QR [18] QR decomposition 414 Virtex 6 vitdec [19] Viterbi decoder (131,81) 1297 Virtex 6…”