ASIC hardware focused comparison for hash functions MD5, RIPEMD-160, and SHS

Satoh, Akashi; Inoue, Toro

doi:10.1109/itcc.2005.92

Cited by 31 publications

(13 citation statements)

References 13 publications

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“…SHA-512 provides the utmost level of integrity preservation among all the hash functions with a large bit length [21], [22]. It produces authentication code of the message [23]. [24].…”

Section: Watermarking With Hashingmentioning

confidence: 99%

A Novel Elliptic Curve Cryptography Based Approach of Re-watermarking for Cheque Truncation System

Mehan¹,

Dhir²,

Brar³

2015

Journal of Discrete Mathematical Sciences and Cryptography

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Cheque Truncation System (CTS) is a technique of preventing tangible movement of cheque by substituting it with a digital image, with an aim for secure and faster clearance. For the first time re-watermarking is applied for authenticating transactions in CTS. Methodology for the proposed approach splits the host image (I h ) into two layers (L). In L 1 cheque details are fused with two image color channels to form a composite message (C m ). Secure hash algorithm (SHA-512) is applied to C m to generate a unique message digest (M d ). Elliptic Curve Digital Signature Algorithm (ECDSA) is applied to M d to create a digital signature. The signature is embedded by exploiting Human Visual System (HVS) color channel sensitivity in equally parted mode. In L 2 , joint secret is established to form key using Elliptic Curve Diffie Hellman Protocol (ECDHP). Advanced Encryption Standard (AES) is applied to user details intricate in the transaction. Encrypted contents are then inserted in L 2 by applying Discrete Cosine Transform (DCT). Experimental results state solution to integrity concerns by using ECDSA with SHA-512, reaction to security issues by AES and the response to key distribution problem by ECDHP. An effective semi-blind CTS is perceived with PSNR between 59-60 dB.

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“…SHA-512 provides the utmost level of integrity preservation among all the hash functions with a large bit length [21], [22]. It produces authentication code of the message [23]. [24].…”

Section: Watermarking With Hashingmentioning

confidence: 99%

A Novel Elliptic Curve Cryptography Based Approach of Re-watermarking for Cheque Truncation System

Mehan¹,

Dhir²,

Brar³

2015

Journal of Discrete Mathematical Sciences and Cryptography

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“…Several hardware techniques have been used to improve SHA performance [4][5][6][7][8][9]. These include the use of parallel counters and carry save adders (CSA) [4][5][6], loop unrolling to mitigate the serial dependence of hash computation [8], delay balancing [5], embedded memories [9] and pipelining [5] to improve throughput.…”

Section: Introductionmentioning

confidence: 99%

“…These include the use of parallel counters and carry save adders (CSA) [4][5][6], loop unrolling to mitigate the serial dependence of hash computation [8], delay balancing [5], embedded memories [9] and pipelining [5] to improve throughput. These techniques require significant additional hardware, resulting in higher area and reduced energy-efficiency.…”

Section: Introductionmentioning

confidence: 99%

18Gbps, 50mW reconfigurable multi-mode SHA Hashing accelerator in 45nm CMOS

Ramanarayanan

Mathew

Sheikh

et al. 2010

2010 Proceedings of ESSCIRC

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A multi-mode Secure Hashing Algorithm (SHA) accelerator is fabricated in 45nm CMOS and occupies 0.0625mm 2 with 18Gbps throughput and total power consumption of 50mW. The reconfigurable hardware accelerator computes SHA-1/224/256/384/512 message-digest using unified SHA bit-slices and configurable compression circuits resulting in 40% area reduction and <3% performance overhead for reconfiguration with 23Gbps peak throughput in SHA-224/256 modes. SHA frequency ranges from 21MHz-1.8GHz across 320mV-1.35V supply voltage range. I. INTRODUCTIONHash functions are important cryptographic primitives used to generate digital fingerprints or signatures [1] in publickey encryption workloads and internet protocols, such as Internet Protocol Security (IPSEC), Message Authentication Codes (MAC) and Secure Sockets Layer (SSL) [2]. The Secure Hashing Algorithms (SHA) family of hashes provides a variety of digest sizes (160b-512b) with varying number of rounds for a variety of applications. While SHA-1 is the most popular hash in use today, the SHA-2 family of hashes (SHA-224/256/384/512) offers enhanced security in the form of higher pre-image and collision resistance at the cost of higher computational complexity. SHA workloads are among the most performance/power-critical workloads due to the iterative nature of hash computation and the high computational complexity of mapping the parallel 64b additions, bitwise rotations and one-way compression functions on a general-purpose microprocessor execution core.

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“…Pramstaller et al [7] present a compact Whirlpool implementation on the Virtex XC2VP40 device, which utilises no Block RAM (BRAM), requires 1,276 slices and operates at 382 Mbps. There has been a significant amount of previous research into hardware architectures of other hash functions implemented on both FPGA [8][9][10][11][12][13][14][15] and ASIC technology [16,17]. These include a highly optimised SHA-512 architecture implemented on a Xilinx XCV1000 FPGA by Grembowski et al which achieves a throughput of 676 Mbps [9].…”

Section: Introductionmentioning

confidence: 99%

“…A number of the same authors have also designed a high-speed unrolled architecture [8], where the SHA-512 functionality is unrolled five times, which reduces the latency by a factor of 5, thus, increasing the overall throughput to 1 Gbps. Satoh and Inoue report a 2.9 Gbps SHA-512 ASIC design [16]. A high-speed ASIC design of the SHA-256 hash function is offered by Helion Technology, which runs at a speed of 1,885 Mbps [17].…”

Section: Introductionmentioning

confidence: 99%

High-speed & Low Area Hardware Architectures of the Whirlpool Hash Function

McLoone

McIvor

2007

J VLSI Sign Process Syst Sign Image Video Technol

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High-speed and low area hardware architectures of the Whirlpool hash function are presented in this paper. A full Look-up Table (LUT) based design is shown to be the fastest method by which to implement the non-linear layer of the algorithm in terms of logic. An unrolled Whirlpool architecture implemented on the Virtex XC4VLX100 device achieves a throughput of 4.9 Gbps. This is faster than a SHA-512 design implemented on the same device and other previously reported hash function architectures. A low area iterative architecture, which utilises 64-bit operations as opposed to full 512-bit operations, is also described. It runs at 430 Mbps and occupies 709 slices on a Virtex X4VLX15. This proves to be one of the smallest 512-bit hash function architectures currently available.

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ASIC hardware focused comparison for hash functions MD5, RIPEMD-160, and SHS

Cited by 31 publications

References 13 publications

A Novel Elliptic Curve Cryptography Based Approach of Re-watermarking for Cheque Truncation System

A Novel Elliptic Curve Cryptography Based Approach of Re-watermarking for Cheque Truncation System

18Gbps, 50mW reconfigurable multi-mode SHA Hashing accelerator in 45nm CMOS

High-speed & Low Area Hardware Architectures of the Whirlpool Hash Function

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