Artificial neural networks in hardware: A survey of two decades of progress

Misra, Janardan; Saha, Indranil

doi:10.1016/j.neucom.2010.03.021

Cited by 557 publications

(311 citation statements)

References 146 publications

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“…A few surveys of neural network hardware have been published in [30]- [34] where several hundred works were listed. Support vector machine (SVM) hardware also seems attractive [35]- [41].…”

Section: Introductionmentioning

confidence: 99%

A K-Means-Based Multi-Prototype High-Speed Learning System with FPGA-Implemented Coprocessor for 1-NN Searching

Koide

Mattausch

2012

IEICE Trans. Inf. & Syst.

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SUMMARYIn this paper, we propose a hardware solution for overcoming the problem of high computational demands in a nearest neighbor (NN) based multi-prototype learning system. The multiple prototypes are obtained by a high-speed K-means clustering algorithm utilizing a concept of software-hardware cooperation that takes advantage of the flexibility of the software and the efficiency of the hardware. The one nearest neighbor (1-NN) classifier is used to recognize an object by searching for the nearest Euclidean distance among the prototypes. The major deficiency in conventional implementations for both K-means and 1-NN is the high computational demand of the nearest neighbor searching. This deficiency is resolved by an FPGA-implemented coprocessor that is a VLSI circuit for searching the nearest Euclidean distance. The coprocessor requires 12.9% logic elements and 58% block memory bits of an Altera Stratix III E110 FPGA device. The hardware communicates with the software by a PCI Express (×4) local-bus-compatible interface. We benchmark our learning system against the popular case of handwritten digit recognition in which abundant previous works for comparison are available. In the case of the MNIST database, we could attain the most efficient accuracy rate of 97.91% with 930 prototypes, the learning speed of 1.3 × 10 −4 s/sample and the classification speed of 3.94 × 10 −8 s/character.

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“…A few surveys of neural network hardware have been published in [30]- [34] where several hundred works were listed. Support vector machine (SVM) hardware also seems attractive [35]- [41].…”

Section: Introductionmentioning

confidence: 99%

A K-Means-Based Multi-Prototype High-Speed Learning System with FPGA-Implemented Coprocessor for 1-NN Searching

Koide

Mattausch

2012

IEICE Trans. Inf. & Syst.

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“…2, June 2012 : 281 -290 282 VLSI and DSP chips. So, many researchers have made great efforts on the realization of neural network (NN) using FPGA technique [4,5].…”

Section: Introductionmentioning

confidence: 99%

Design of FPGA Based Neural Network Controller for Earth Station Power System

et al. 2012

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“…As an alternative to conventional sorting techniques, a neural network design resulting from the harmony theory has been proposed for the sorting operation [7]. Neural network hardware can be implemented with parallel architecture using VLSI and FPGA technology, and this is highly desirable for high-speed computation [8][9][10][11].…”

Section: Introductionmentioning

confidence: 99%

Neural Network Based Order Statistic Processing Engines

Unluturk

Saniie²

2012

JSIP

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Order statistic filters are used often in the applications of science and engineering problems. This paper investigates the design and training of a feed-forward neural network to approximate minimum, median and maximum operations. The design of order statistic neural network filtering (OSNNF) is further refined by converting the input vectors with elements of real numbers to a set of inputs consisting of ones and zeros, and the neural network is trained to yield a rank vector which can be used to obtain the exact ranked values of the input vector. As a case study, the OSNNF is used to improve the visibility of target echoes masked by clutter in ultrasonic nondestructive testing applications.

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Artificial neural networks in hardware: A survey of two decades of progress

Cited by 557 publications

References 146 publications

A K-Means-Based Multi-Prototype High-Speed Learning System with FPGA-Implemented Coprocessor for 1-NN Searching

A K-Means-Based Multi-Prototype High-Speed Learning System with FPGA-Implemented Coprocessor for 1-NN Searching

Design of FPGA Based Neural Network Controller for Earth Station Power System

Neural Network Based Order Statistic Processing Engines

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